Back Gate Dielectric Structure for Void-Free Memory Cell Scaling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining higher degrees of integration and reliability due to limitations in down-scaling and the formation of process defects such as unintended voids or seams during the fabrication of vertical channel transistors.
Innovation Solution
The semiconductor memory device incorporates a conductive line with channel regions and contact plugs arranged in a specific configuration, along with a back gate electrode and dielectric film that includes vertical and horizontal extension portions to mitigate process defects and enable down-scaling and higher integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are down-scaled to achieve higher integration, then device density increases, but process defects such as unintended voids or seams form during fabrication
Solution Approach 1:
The gate dielectric film is segmented into multiple portions: a first portion conformally covering the sidewalls of the gate electrode, a second portion filling the gap between adjacent gate electrodes, and a third portion covering the upper surface. This segmentation allows each portion to be optimized independently for its specific function, preventing void formation while maintaining conformal coverage.
Solution Approach 2:
The gate dielectric film is formed to extend between adjacent gate electrodes before the semiconductor fins are fully processed. This preliminary action ensures that the dielectric material is already in place to prevent void formation during subsequent processing steps, particularly during the formation of contact holes or interlayer structures.
2Manufacturing precision
If gate dielectric film is conformally deposited to cover sidewalls, then coverage is improved, but unintended voids or seams form in the process
Solution Approach 1:
The gate dielectric film structure transitions from a simple vertical sidewall coating to a three-dimensional continuous structure that extends horizontally between gate electrodes and vertically along sidewalls. This dimensional extension ensures coverage of previously inaccessible regions without creating voids, as the dielectric material forms a bridging structure between adjacent gates.
Solution Approach 2:
The gate dielectric film merges the coverage functions of multiple surfaces: sidewalls, upper surfaces, and gap regions between adjacent gate electrodes are covered by a continuous, integrated dielectric structure rather than separate deposition steps, eliminating seams and voids at the interfaces.
3Productivity
If components are arranged in narrow and long space for down-scaling, then integration increases, but fabrication process becomes more difficult
Solution Approach 1:
The gate dielectric film structure serves multiple functions simultaneously: it provides electrical isolation between adjacent gate electrodes, mechanically supports the narrow spacing structure, prevents void formation during subsequent processing, and maintains conformal sidewall coverage. This multi-functionality simplifies the overall fabrication process despite the narrow and long spatial arrangement.
Data Source
AI summary
A semiconductor memory device includes a conductive line extending in a first direction, first and second channel regions connected to the conductive line, contact plugs apart from the conductive line in a vertical direction with the first and second channel regions therebetween, a back gate electrode extending in a second direction perpendicular to the first direction between the first and second channel regions, and a back gate dielectric film covering surfaces of the back gate electrode, wherein the back gate dielectric film includes a vertical extension portion arranged between the back gate electrode and each of the first and second channel regions to cover sidewalls of the back gate electrode, and a horizontal extension portion connected integrally to the vertical extension portion and covering the back gate electrode at one position selected from a first position facing the conductive line and a second position facing the contact plugs.