Back-Gate Biased Differential Pair for Low-Noise MOS Amplification
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Solution Overview
Problem
Existing differential circuits, such as operational amplifiers, face challenges in reducing noise in output signals, particularly due to limitations in transconductance and 1/f noise, which affect the stability and efficiency of electronic devices like liquid crystal driving devices.
Innovation Solution
A differential circuit design that incorporates a differential pair of MOS transistors with a back gate bias circuit, where a bias voltage closer to the power supply voltage is applied to the back gates of the transistors, increasing transconductance and reducing noise. This design also employs a current adjustment unit and specific transistor configurations to manage transconductance and 1/f noise, including the use of high and low concentration transistors and embedded channel types to optimize signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional operational amplifier is used, then the device can perform basic amplification functions, but the noise of output signals cannot be sufficiently reduced
Solution Approach 1:
The patent applies parameter changes by adjusting the back gate-to-source voltage (Vbs) of the MOS transistors in the differential pair. By setting Vbs to a specific range (0.1V to 0.5V), the transconductance (gm) is optimized, which directly reduces the noise of output signals. This parameter optimization resolves the contradiction between maintaining signal quality and reducing noise without requiring complex circuit modifications.
2Object-affected harmful factors
If the transconductance of MOS transistors is increased to reduce noise, then the noise reduction improves, but the power consumption increases
Solution Approach 1:
The patent optimizes the back gate-to-source voltage (Vbs) parameter to achieve the noise reduction goal while controlling power consumption. By setting Vbs within the range of 0.1V to 0.5V, the transconductance is enhanced sufficiently for noise reduction without excessively increasing the drain current and power consumption. This controlled parameter adjustment resolves the contradiction between noise reduction and power consumption.
Solution Approach 2:
The patent applies partial action by adjusting only the back gate voltage parameter rather than increasing the supply voltage or drain current to reduce noise. This partial adjustment of Vbs provides the necessary transconductance enhancement for noise reduction while avoiding the excessive power consumption that would result from more aggressive approaches.
3Object-affected harmful factors
If the back gate bias voltage is set closer to the power supply voltage to increase transconductance, then the noise reduces, but the risk of parasitic diode conduction increases
Solution Approach 1:
The patent carefully optimizes the back gate-to-source voltage (Vbs) parameter within a specific range (0.1V to 0.5V) that enhances transconductance for noise reduction while maintaining a safe margin below the parasitic diode conduction threshold. This controlled parameter adjustment resolves the contradiction between noise reduction and transistor operation stability.
Solution Approach 2:
The patent applies preliminary anti-action by preemptively limiting the back gate bias voltage to prevent parasitic diode conduction before it occurs. By setting Vbs to a maximum of 0.5V (well below the typical 0.7V diode turn-on voltage), the design proactively prevents the harmful effect of parasitic diode conduction while still achieving the desired noise reduction through enhanced transconductance.
Data Source
AI summary
A differential circuit includes a differential pair and a back gate bias circuit. The differential circuit includes a first MOS transistor and a second MOS transistor provided between a first power supply line, to which a first power supply voltage is applied, and a second power supply line, to which a second power supply voltage is applied. The back gate bias circuit applies a bias voltage closer to the first power supply voltage than source potentials of the first MOS transistor and the second MOS transistor to back gates of the first MOS transistor and the second MOS transistor.