Back Gate Doping for SRAM Logic Coexistence
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Solution Overview
Problem
Doping fluctuations pose a significant challenge for static random access memory (SRAM) scaling, particularly at the 45 nm node, leading to threshold mismatch and fail rates that are beyond practical repair, due to the scaling of doping atoms and their distribution in shrinking feature sizes.
Innovation Solution
A semiconductor structure with double gated field effect transistors (FETs) in both logic and SRAM regions, where the back gate in the SRAM region is more heavily doped than in the logic region, utilizing an ultra-thin body planar fully depleted semiconductor-on-insulator (SOI) material, and employing heavily doped back gates in SRAM regions with undoped channels to control short channel effects, while lightly doping logic region back gates to minimize additional capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the back gate in SRAM region is heavily doped to control short channel effects and reduce doping fluctuations, then the reliability of SRAM devices is improved, but the capacitance increases affecting logic device performance
Solution Approach 1:
The patent implements different doping concentrations for back gates in different device regions. Specifically, the back gate in the SRAM region is heavily doped (1E19 to 1E21 atoms/cm³) to control short channel effects and reduce doping fluctuations, while the back gate in the logic region is lightly doped (1E16 to 1E18 atoms/cm³) to minimize capacitance effects. This local differentiation allows each region to be optimized for its specific functional requirements without compromising the other.
2Productivity
If feature sizes are shrunk to increase device density, then the productivity is improved, but the doping fluctuations increase causing threshold mismatch
Solution Approach 1:
The patent changes the doping concentration parameter of the back gate to compensate for doping fluctuations in scaled devices. By heavily doping the back gate in the SRAM region (1E19 to 1E21 atoms/cm³), the patent reduces the relative impact of doping statistical variations that occur when feature sizes are shrunk. This parameter change allows maintaining tight threshold voltage control even as device dimensions are reduced to increase density.
Solution Approach 2:
The patent introduces back gate control as an additional degree of freedom to manage doping fluctuations. Instead of relying solely on front gate control in the planar dimension, the patent utilizes the vertical dimension by implementing a back gate that can be independently doped and biased. This extra dimension of control provides an additional mechanism to counteract doping variations and maintain threshold precision in scaled devices.
3Reliability
If the channel is doped to control short channel effects in logic devices, then the short channel control is improved, but the doping fluctuations are exacerbated
Solution Approach 1:
The patent introduces the back gate as an intermediary element to control short channel effects without requiring heavy channel doping. The heavily doped back gate in the SRAM region creates a strong electric field that extends into the channel, providing short channel control through the back interface. This mediator approach allows achieving short channel control while keeping the channel itself relatively lightly doped, thus avoiding the threshold mismatch problems that would result from heavy channel doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses doping fluctuation issues by maximizing back gate control in SRAM regions and minimizing performance degradation in logic devices, enabling improved performance and reliability in both SRAM and logic devices through optimized doping levels and biasing.
Implementation Method 1
the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions
Implementation Method 2
In order to control short channel effects, the FET device within the logic device region includes a doped channel
Implementation Method 3
an ultra-thin (on the order of about 10 nm to about 20 nm) body planar fully depleted semiconductor-on-insulator (SOI) material
Data Source
AI summary
A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.