Back Gate Contact FETs with Buried High Resistivity Layer
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Solution Overview
Problem
Bulk silicon substrates suffer from poor device isolation due to harmonic generation, and the presence of a trap-rich layer prevents the formation of body contacts, limiting the performance of field effect transistors compared to silicon-on-insulator (SOI) substrates.
Innovation Solution
A semiconductor structure with a buried high resistivity polysilicon layer separated from the buried oxide layer by a single crystalline semiconductor region, enabling the formation of body bias regions and improving device isolation, linearity, and RF performance through the use of back gate contacts and shallow trench isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bulk silicon substrate is used, then cost is reduced, but device isolation from harmonic generation deteriorates
Solution Approach 1:
The substrate is segmented into distinct functional layers: a bulk silicon substrate providing mechanical support and cost benefits, a buried oxide layer providing electrical isolation, and a device layer containing the active devices. This segmentation allows the bulk substrate to provide cost advantages while the oxide layer eliminates harmonic generation interference.
Solution Approach 2:
A buried oxide layer is introduced as an intermediary between the bulk silicon substrate and the device layer. This oxide layer acts as a mediator that provides electrical isolation and prevents harmonic generation from the bulk substrate while allowing the device to function properly on a cost-effective bulk substrate.
2Object-generated harmful factors
If trap rich layer is used as handle substrate, then isolation is improved, but body contact formation is prevented
Solution Approach 1:
The body contact is formed in a different dimensional space - specifically, in the bulk silicon substrate below the oxide layer rather than in the oxide layer itself or at the device interface. This allows body contact formation in the n-type bulk substrate while maintaining the isolation properties of the trap-rich oxide layer.
Solution Approach 2:
The substrate structure is segmented into an upper device region with oxide isolation and a lower bulk region where body contacts can be formed. This segmentation allows the oxide layer to provide isolation where needed while the bulk silicon region provides pathways for body contact formation.
3Reliability
If SOI substrate is used, then device performance is improved, but substrate cost increases
Solution Approach 1:
The oxide layer thickness parameter is optimized to balance performance and cost. By controlling the oxide thickness to be sufficient for isolation but not excessively thick, the device achieves SOI-like performance benefits while maintaining cost-effectiveness compared to fully depleted SOI structures.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors with back gate contact and buried high resistivity layer and methods of manufacture. The structure includes: a handle wafer comprising a single crystalline semiconductor region; an insulator layer over the single crystalline semiconductor region; a semiconductor layer over the insulator layer; a high resistivity layer in the handle wafer, separated from the insulator layer by the single crystalline semiconductor region; and a device on the semiconductor layer.