Back-Gate FET Control for Constant Drain Current and Higher Gain
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Solution Overview
Problem
In field-effect transistors, parasitic effects cause an increase in drain current in the saturation region as drain-source voltage increases, leading to reduced small signal drain-source resistance and intrinsic gain, making it difficult to achieve high voltage gain in scaled CMOS processes.
Innovation Solution
A field-effect transistor system with a back-gate terminal that can be adjusted by a control unit using back-gate voltage, which compensates for parasitic effects by controlling the back-gate voltage based on gate-source and drain-source voltages to set a constant drain current, thereby increasing the intrinsic gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor scaling is increased in CMOS processes, then device size is reduced and integration density is improved, but parasitic effects increase causing drain current to rise in saturation region
Solution Approach 1:
The patent implements a feedback control mechanism where the back-gate voltage is dynamically adjusted based on the drain current in the saturation region. The control unit monitors the drain current and modifies the back-gate voltage to counteract the parasitic-induced current increase, thereby stabilizing the output characteristic curve and maintaining constant drain current despite scaling effects.
Solution Approach 2:
The patent changes the electrical parameters of the field-effect transistor by applying an adjustable back-gate voltage. This additional voltage parameter allows independent control of the channel conductivity, enabling compensation for parasitic effects without altering the physical transistor dimensions or standard operating voltages.
2Reliability
If drain current increases in saturation region due to parasitic effects, then transistor conductance is improved, but small signal drain-source resistance decreases and intrinsic gain is reduced
Solution Approach 1:
The control unit continuously monitors the drain current and adjusts the back-gate voltage to maintain a stable drain current in the saturation region. This feedback mechanism prevents the parasitic-induced current increase that would otherwise reduce the small signal drain-source resistance and intrinsic gain, thereby preserving the transistor's voltage amplification capability.
Solution Approach 2:
The back-gate voltage acts as a counterbalancing control parameter that offsets the harmful parasitic effects. By applying an appropriate back-gate voltage, the system compensates for the unwanted drain current increase, effectively counterweighting the parasitic influence and maintaining optimal transistor performance for high gain applications.
3Manufacturing precision
If complex circuit topologies with multiple field-effect transistors are used to achieve high voltage gain, then voltage gain is improved, but device complexity and stacking requirements increase
Solution Approach 1:
The patent extracts the gain-enhancement function from complex multi-transistor circuit topologies and implements it within a single field-effect transistor by utilizing the back-gate terminal. This extraction approach allows the transistor itself to provide the necessary voltage gain characteristics without requiring external complex circuitry or transistor stacking.
Solution Approach 2:
The back-gate terminal provides multi-functionality by enabling both standard transistor operation and active compensation of parasitic effects through a single device structure. This universal approach allows the same transistor to achieve high voltage gain without requiring separate dedicated circuits for gain enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for parasitic effects, resulting in increased small signal drain-source resistance and improved intrinsic gain, allowing for higher voltage gain without the need for transistor stacking, even in scaled CMOS technologies.
Implementation Method 1
a field-effect transistor having a back-gate terminal which can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage being in addition present at the field-effect transistor
Data Source
AI summary
A field-effect transistor system is provided that comprises a field-effect transistor having a back-gate terminal that can be adjusted by a back-gate voltage, a gate-source voltage and a drain-source voltage additionally being present at the field-effect transistor, and a drain current flowing through the field-effect transistor. In addition, the field-effect transistor system includes a control unit connected to the back-gate terminal, which unit is set up to set the drain current flowing through the field-effect transistor to a setpoint current via a controlling of the back-gate voltage at the back-gate terminal, the controlling of the back-gate voltage taking place as a function of at least the gate-source voltage. In addition, a method is provided for setting a drain current of a field-effect transistor.