Active Matrix Substrate Back Gate Inspection TFT Thermal Stability
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Solution Overview
Problem
In liquid crystal display panels, the inspection TFTs positioned near the semiconductor chip are prone to temperature-related shifts in characteristics, making it difficult to maintain a reliable OFF state, which can lead to reduced reliability and potential failures in the active matrix substrate.
Innovation Solution
The active matrix substrate design includes inspection TFTs with a back gate structure, positioned within the semiconductor chip mounting area, where the back gate electrode is positioned on top of the semiconductor layer with an insulation layer in between, allowing for independent control of the threshold voltage and maintaining the OFF state even under high temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the inspection TFT is positioned within the semiconductor chip mounting area to narrow the non-display area, then the frame area is reduced, but the inspection TFT is exposed to high temperatures causing threshold voltage shifts and difficulty in maintaining OFF state
Solution Approach 1:
The patent applies local quality by giving the inspection TFT a different structure (back gate structure) compared to conventional TFTs, specifically positioning the gate electrode on the opposite side of the semiconductor layer to create localized thermal isolation and maintain stable electrical characteristics in high-temperature environments
Solution Approach 2:
The patent inverts the conventional TFT structure by placing the gate electrode on the back side of the semiconductor layer rather than the front side, creating a back gate structure that fundamentally changes the thermal and electrical characteristics of the inspection TFT
2Area of stationary object
If the inspection TFT is positioned at a lower portion of the semiconductor chip to further narrow the frame area, then the device size is reduced, but the temperature at the inspection TFT location becomes excessively high causing characteristic shifts
Solution Approach 1:
The back gate structure creates localized structural differences in the inspection TFT region, positioning the gate electrode on the opposite side of the semiconductor layer to establish a thermal barrier that isolates the inspection TFT from high temperatures generated by the semiconductor chip
Solution Approach 2:
The patent transitions from a conventional planar gate structure to a three-dimensional back gate configuration, positioning the gate electrode in a different spatial dimension (on the opposite side of the semiconductor layer) to achieve thermal management without compromising electrical performance
Data Source
AI summary
Provided is an active matrix substrate (1001) that includes multiple inspection TFTs (10Q) that are arranged in a non-display area (900), and an inspection circuit (200) that includes multiple inspection TFTs (10Q). At least one or more of the multiple inspection TFTs (10Q) are arranged within a semiconductor chip mounting area (R) in which a semiconductor chip is mounted. Each of the multiple inspection TFTs (10Q) includes a semiconductor layer, a lower gate electrode (FG) that is positioned on a side of the substrate of the semiconductor layer with a gate insulation layer in between, an upper gate electrode (BG) that is positioned on a side opposite to the side of the substrate of the semiconductor layer with an insulation layer including a first insulation layer in between, and a source electrode and a drain electrode that are connected to the semiconductor layer.