Back-Gate Inverter for High Voltage Tolerance
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Solution Overview
Problem
Traditional inverter circuits are unable to withstand high input voltages without incurring increased power consumption, larger circuit area, and reduced speed, and they struggle to set the threshold voltage at the middle of high and low levels due to limitations in gate-oxide voltage ratings of MOSFETs.
Innovation Solution
The proposed inverter design applies input voltage to the back-gates of transistors instead of the gates, using a bias circuit to adjust the threshold voltage, allowing the inverter to handle higher input voltages and improve electrostatic discharge tolerance, with transistors processed in a silicon-on-insulator (SOI) process and thicker back-gate isolation layers for enhanced robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional CMOS inverter is used with higher input voltages, then the inverter can handle higher input voltages, but the gate-oxide voltage rating is exceeded causing damage
Solution Approach 1:
The patent divides the voltage handling function between two separate paths: the gate terminal (handled by thin-oxide transistors for low voltage control) and the back-gate terminal (handled by thick-oxide transistors for high voltage tolerance). This segmentation allows each terminal to be optimized for its specific voltage range, enabling the inverter to accept high input voltages without exceeding gate-oxide ratings.
Solution Approach 2:
The back-gate serves as an intermediary terminal that receives high input voltages through thick-oxide transistors and transfers the voltage control function to the channel without exposing the gate-oxide to high voltages. The thick-oxide back-gate isolation layer acts as a protective mediator that withstands high voltages while the thin-oxide gate isolation layer remains within safe voltage limits.
2Adaptability or versatility
If resistive divider is added to cope with high input voltages, then voltage division is achieved, but power consumption increases and circuit area increases
Solution Approach 1:
The back-gate terminal is integrated into the existing transistor structure, allowing the same transistor to serve dual functions: the gate terminal for normal control operations and the back-gate terminal for high voltage input handling. This multi-functionality eliminates the need for separate resistive dividers or voltage scaling circuits, reducing overall circuit area while maintaining high voltage tolerance.
3Adaptability or versatility
If resistive divider is added to cope with high input voltages, then voltage division is achieved, but switching speed is reduced due to RC filtering
Solution Approach 1:
The patent extracts the voltage division function from the signal path by applying it directly to the back-gate terminal instead of using resistive dividers in the main signal path. This removes the RC filtering effect that would otherwise slow down switching operations, as the back-gate voltage control is applied in parallel without interfering with the fast gate-controlled switching dynamics.
4Adaptability or versatility
If extended-drain or LDMOS transistor is used to limit voltages, then high voltage tolerance is achieved, but threshold voltage setting at middle level becomes impossible
Solution Approach 1:
The patent employs dynamic voltage control of the back-gate through a bias circuit that adjusts the back-gate voltage based on the input voltage level. This dynamic adjustment allows the inverter threshold to be set at the middle level (between high and low input voltages) by controlling the back-gate voltage, overcoming the static voltage clipping limitation of extended-drain or LDMOS transistors where the threshold cannot be properly centered.
Data Source
AI summary
An inverter is presented. The inverter may be configured to receive an input voltage at an input node of the inverter, and to generate an output voltage at an output node of the inverter. The inverter may comprise a first transistor coupled between a supply node and the output node of the inverter. Further, the inverter may comprise a second transistor coupled between the output node of the inverter and a reference node. The input node of the inverter may be coupled to a back-gate of the first transistor and to a back-gate of the second transistor.