Back-Gate Level Shifter Latch for High-Voltage Signal Translation
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Solution Overview
Problem
Existing level shifter circuits face challenges in efficiently shifting signals between voltage domains, particularly when dealing with higher voltage differences, resulting in increased signal delay and power dissipation.
Innovation Solution
A level shifter circuit utilizing multi-gate transistors with back gates and front gates, configured in a cross-coupled latch circuit, allowing for higher voltage shifts with reduced power dissipation and implementation area, by using 1.0 V and 1.8 V transistors to achieve shifts up to lithium-ion battery voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional topologies with standard transistors are used for level shifting, then the circuit is simple, but signal delay increases and power dissipation increases when shifting to higher voltage domains
Solution Approach 1:
The patent changes the operating parameters of transistors by applying different voltage levels to front gates and back gates independently. This allows standard transistors to operate in high-voltage domains without requiring specialized high-voltage devices, thereby reducing signal delay while maintaining circuit simplicity.
Solution Approach 2:
The patent segments the gate control into two independent parts: front gate and back gate. This segmentation allows separate control of threshold voltage and channel conductivity, enabling fast switching performance in high-voltage domains using standard transistor structures.
2Adaptability or versatility
If special high-voltage devices such as LDMOS are used for level shifting to higher voltage domains, then voltage shifting capability is improved, but power dissipation increases and circuit complexity increases
Solution Approach 1:
The patent changes the voltage parameters applied to transistor gates dynamically. By controlling back gate voltage independently, standard transistors can adapt to different voltage domains (1.0V, 1.8V, 2.5V, 3.3V, 3.7V, 4.2V) without requiring specialized high-voltage devices like LDMOS, thereby reducing power dissipation while maintaining voltage shifting capability.
Solution Approach 2:
The patent makes standard transistors universal by enabling them to operate across multiple voltage domains through independent front gate and back gate control. This eliminates the need for different transistor types for different voltage levels, reducing both power dissipation and device complexity.
3Adaptability or versatility
If special high-voltage devices are used for level shifting, then voltage shifting capability is improved, but device complexity increases
Solution Approach 1:
The patent uses parameter changes (different voltage levels on front and back gates) to enable standard transistors to handle high voltage shifts. This approach maintains device simplicity while achieving the ability to shift signals across multiple voltage domains up to lithium-ion battery levels.
4Device complexity
If standard transistors are used for high voltage shifts, then device simplicity is maintained, but voltage shifting capability is limited
Solution Approach 1:
The patent overcomes the voltage limitation of standard transistors by changing the control parameters independently at front and back gates. The back gate controls threshold voltage to prevent breakdown, while the front gate enables full voltage swing, allowing standard transistors to achieve high voltage shifting capability without structural modifications.
Data Source
AI summary
A level shifter circuit includes: first and second output voltage supplies, and a latch circuit comprising a first logic gate having at least two first transistors, each of which having front and back gates, a first main input terminal, a first secondary input terminal, and a first output terminal, a second logic gate having at least two second transistors, each of which having front and back gates, a second main input terminal, a second secondary input terminal, and a second output terminal, and a latch output terminal, the first secondary input terminal being coupled to the second output terminal, the second secondary input terminal being coupled to the first output terminal, the latch circuit having a first state in which the latch output terminal is coupled to the first output voltage supply, and a second state in which the latch output terminal is coupled to the second output voltage supply.


