Back-Gate Memory Cell Layout for Dense Vertical Channel Arrays
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Solution Overview
Problem
Existing semiconductor devices face limitations in integration density and electric characteristics due to the high cost of fine pattern forming technology, which restricts the integration of two-dimensional devices.
Innovation Solution
A semiconductor memory device design featuring bit lines, active patterns, back-gate electrodes, word lines, and contact patterns arranged in specific configurations, along with insulating and gate structures, to enhance integration density and electric performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area occupation by unit memory cell
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertical channel field-effect transistors. The vertical channel extends in the third dimension (vertical direction), allowing multiple channels to be stacked vertically, thereby increasing integration density without requiring finer lateral patterning. This dimensional transition enables higher integration while maintaining manufacturability through established vertical fabrication techniques.
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but process equipment cost increases extremely
Solution Approach 1:
By moving to vertical channel FETs, the patent achieves higher integration density through vertical stacking rather than lateral miniaturization. This approach uses existing patterning equipment capabilities while exploiting the vertical dimension for increased device density, thereby avoiding the need for extremely expensive advanced lithography equipment.
Solution Approach 2:
The vertical channel structure allows multiple active patterns and gate electrodes to be nested or stacked in the vertical direction. This nesting approach increases the number of functional elements within a given lateral footprint without requiring proportionally more complex patterning equipment, thus improving integration density while controlling manufacturing costs.
3Quantity of substance
If vertical channel field-effect transistors are used, then integration density increases, but device structure complexity increases
Solution Approach 1:
The vertical channel FET is segmented into distinct functional regions: active patterns forming the channel, gate electrodes wrapping around the channel, and insulating patterns providing electrical isolation. This segmentation allows each component to be optimized independently while maintaining overall structural efficiency, managing device complexity through modular design.
Solution Approach 2:
The gate electrode structure serves multiple functions: it controls the channel current, provides electrical isolation through integrated insulating patterns, and enables vertical stacking for higher integration. This multi-functionality reduces the need for separate components, thereby increasing integration density while managing overall device complexity.
4Quantity of substance
If more active patterns are integrated, then integration density improves, but leakage current increases
Solution Approach 1:
Insulating patterns are extracted and strategically positioned between adjacent active patterns and around the gate electrode. These insulating patterns are removed from the conductive path, creating electrical isolation that prevents leakage current between neighboring vertical channels, thereby enabling higher integration density without proportionally increasing leakage.
Solution Approach 2:
The insulating patterns act as intermediary elements between adjacent active patterns. These intermediaries provide electrical isolation and prevent direct current leakage pathways between neighboring channels, allowing more active patterns to be integrated closely together while maintaining low leakage current performance.
Data Source
AI summary
A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.