Back-Gate Memory Transistor Structure to Mitigate Short Channel Effects
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Solution Overview
Problem
The reduction in device size of semiconductor memory devices leads to the short channel effect (SCE), which compromises the performance and density of memory devices, as the effective channel length is reduced, affecting the transistor's functionality.
Innovation Solution
The implementation of a memory device with a back-gate thin-film transistor structure, where the effective channel length is increased in the vertical direction by forming conductive layers and gate dielectric layers in a conformal manner with connected segments, allowing better control over the channel layer across its length without significantly increasing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If device size is reduced to increase memory density, then device area is decreased, but short channel effect worsens due to reduced effective channel length
Solution Approach 1:
The patent introduces a back-gate structure that extends the gate control into the vertical dimension beneath the channel layer. This allows the effective channel length to be increased in the vertical direction while maintaining a compact planar footprint, thereby resolving the contradiction between small device area and adequate channel length for reliable transistor operation
2Reliability
If effective channel length is increased in vertical direction, then transistor control capability is improved, but device complexity increases due to additional conformal layer formation
Solution Approach 1:
The patent combines the back-gate structure with existing interconnect layers (first and second metallization layers) to form the gate region. By merging the back-gate function with available interconnect structures and using conformal deposition techniques for gate dielectric and channel layers, the design achieves enhanced control capability while minimizing additional process complexity
Data Source
AI summary
A method includes: forming an interconnect structure over a substrate, the forming of the interconnect structure includes forming a memory device including a transistor. The forming of the interconnect structure includes: forming a first metallization layer and a second metallization layer over the first metallization layer; forming a gate region of the transistor in at least one of the first and second metallization layers; etching a trench disposed in the second metallization layer and exposing the gate region; depositing a gate dielectric layer in the trench over the gate region; depositing a channel layer in the trench over the gate dielectric layer; and forming two source/drain regions of the transistor over the channel layer on opposite sides of the trench. At least one of the gate region and the channel layer includes two first segments extending in the trench, wherein the first segments are parallel with each other.