Back-Gate Oxide TFT Gate Driver for Residual Charge Discharge

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Solution Overview

Problem

The challenge is to quickly remove residual charge from an oxide semiconductor gate driver panel in liquid crystal display devices when power is turned off, while reducing the size and manufacturing cost of the active matrix substrate and its components.

Innovation Solution

An active matrix substrate with a gate driver incorporating a multi-stage shift register, featuring oxide semiconductor TFTs with a back-gate structure, allows for quick discharge of residual charge by increasing leakage current when the gate is off, eliminating the need for generating two distinct gate on-potentials, thus reducing the power supply circuit area and manufacturing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a monolithic gate driver with oxide semiconductor TFTs is used, then high-speed operation is achieved, but residual charge cannot be quickly discharged when power is turned off

Engineering Contradiction:
Improveoperation speedVSAvoidcharge discharge time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The gate driver TFTs are segmented into two types: pixel TFTs with single-gate structure and circuit TFTs with back-gate structure. This segmentation allows different discharge paths for pixel regions and gate driver regions, enabling quick discharge of residual charge from floating nodes in the gate driver while maintaining high-speed operation characteristics of oxide semiconductor TFTs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The back-gate electrode serves as an intermediary discharge path for floating charge in the gate driver circuit. By applying a discharge potential to the back-gate electrode, charge can be quickly removed from floating nodes through the back-gate channel, acting as a mediator between the floating charge and the ground potential.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If two distinct gate on-potentials are generated for clock and clear signals, then charge discharge control is improved, but power supply circuit area and manufacturing cost increase

Engineering Contradiction:
Improvecharge discharge controlVSAvoidpower supply circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

A single gate on-potential is used for both clock and clear signals, making the power supply circuit universal. The back-gate structure enables the clear signal to effectively discharge charge from floating nodes even with the same potential level as the clock signal, eliminating the need for separate potential generation circuits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If oxide semiconductor TFTs with small off-leakage current are used, then low power consumption is achieved, but floating charge cannot be quickly discharged

Engineering Contradiction:
Improvepower consumptionVSAvoidcharge discharge time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The back-gate structure provides dynamic control over the discharge path. During normal operation, the back-gate maintains low leakage current for power savings. During discharge operations, the back-gate potential is dynamically changed to create a low-resistance discharge path for rapid charge removal, achieving both low power consumption and fast discharge.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10629630B2Active matrix substrate, and liquid crystal display device provided with active matrix substrate
Publication Date: 2020.04.21 SHARP KK
  • US10629630B2 patent drawing
  • US10629630B2 patent drawing
  • US10629630B2 patent drawing

AI summary

An active matrix substrate is provided with a gate driver including a multi-stage shift register (240). Each stage of the multi-stage shift register has a plurality of oxide semiconductor TFTs, a first input terminal for receiving a set signal, a second input terminal for receiving a clock signal, a third input terminal for receiving a clear signal, and an output terminal for outputting a gate output signal to one of the plurality of gate bus lines. The clock signal and the clear signal have the same high-level potential, and the clock signal and the clear signal have the same low-level potential. The plurality of oxide semiconductor TFTs include a first TFT (101) having a back-gate structure. The main gate electrode of the first TFT (101) is coupled to the third input terminal or a negative power supply voltage VSS. The back-gate electrode of the first TFT has a potential set to a positive power supply voltage VDD or a ground potential GND.