Back Gate Sandwich Fin SOI Structure for Fin Collapse Prevention
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Solution Overview
Problem
Current semiconductor technologies face challenges such as short channel effects, high manufacturing costs, and reliability issues with ultra-thin body and fin field effect transistor (FinFET) devices due to continuous scaling down, particularly with the thinning of fin structures and self-heating problems in expensive ET-SOI substrates.
Innovation Solution
The semiconductor arrangement employs a sandwich fin configuration with a back gate interposed between fins on a semiconductor on insulator (SOI) substrate, allowing for effective threshold voltage control and improved reliability by using a back gate as a support for the fins, while maintaining existing FinFET manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If fins are made thinner to continue scaling down, then device density is improved, but fins tend to collapse during manufacture
Solution Approach 1:
The fin structure is segmented by introducing a back gate that divides the fin into two portions, with the back gate acting as a support structure between the fins. This segmentation prevents the fin from collapsing while maintaining thin dimensions for continued scaling.
Solution Approach 2:
A back gate dielectric layer is introduced as an intermediary between the back gate and the fin, enabling proper electrical isolation and structural support. This intermediary layer allows the thin fin to maintain its shape during manufacturing while preserving device density.
2Ease of operation
If back gate is positioned close to fins for better control, then threshold voltage control is improved, but risk of fin collapse increases
Solution Approach 1:
The back gate dielectric layer serves as a critical intermediary that enables the back gate to be positioned close to the fin for effective threshold voltage control while simultaneously providing structural support that prevents fin collapse. The dielectric layer bridges the gap between electrical control requirements and mechanical stability needs.
Data Source
AI summary
Semiconductor arrangements and methods for manufacturing the same are provided. In one embodiment, the arrangement may include: a semiconductor on insulator (SOI) substrate, comprising a base substrate, a buried dielectric layer, and a SOI layer; a back gate formed on the SOI substrate and passing through the buried dielectric layer to be in electric contact with the base substrate; fins formed from the SOI layer on opposite sides of the back gate; and back gate dielectric layers interposed between the back gate and the respective fins.