Back Gate Select Transistor for eDRAM

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Solution Overview

Problem

Embedded DRAMs face challenges in achieving low off-current and fast operation without the need for overdrive voltage, which increases power consumption and manufacturing complexity due to the absence of a 3D select transistor and high threshold voltage requirements.

Innovation Solution

A dual gate structure is introduced for the select transistor, incorporating a back gate to control the threshold voltage and reduce leakage current, allowing for low off-current during retention and quick operation during read/write without overdrive voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If a long channel select transistor is used to reduce leakage current, then off current is reduced, but area increases and channel length cannot be shortened to save area

Engineering Contradiction:
Improveleakage currentVSAvoidtransistor area
Core Design Contradiction:
Object-generated harmful factorsVSArea of stationary object

Solution Approach 1:

The transistor channel is divided into two independent gates (front gate and back gate) that can be controlled separately. This segmentation allows independent optimization of different transistor states: the back gate sets a high threshold voltage to reduce leakage in off-state, while the front gate provides overdrive voltage for fast switching in on-state, eliminating the need for a long channel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The threshold voltage of the select transistor is made dynamic and adjustable through dual gate control. The back gate voltage can be adjusted to dynamically change the threshold voltage, enabling the transistor to operate in different modes (high threshold for low leakage, low threshold for fast switching) without requiring a long channel structure.

Inventive Principle:
Principle #15Dynamics

2Object-generated harmful factors

If a high threshold voltage is used to reduce off current, then leakage is reduced, but on current decreases and operation speed slows down

Engineering Contradiction:
Improveoff currentVSAvoidoperation speed
Core Design Contradiction:
Object-generated harmful factorsVSProductivity

Solution Approach 1:

The threshold voltage is made dynamically adjustable through dual gate control. During retention mode, the back gate is biased to provide high threshold voltage for low leakage. During read/write operations, the back gate bias is adjusted to reduce threshold voltage, enabling fast switching and high on-current without increasing leakage in standby mode.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The control of threshold voltage is segmented between two gates: the back gate primarily controls the threshold voltage level, while the front gate provides the overdrive voltage for fast switching. This segmentation allows independent optimization of threshold voltage and switching speed, resolving the trade-off between low off-current and fast operation.

Inventive Principle:
Principle #1Segmentation

3Productivity

If overdrive voltage is used to achieve fast operation, then switching speed improves, but power consumption increases

Engineering Contradiction:
Improveswitching speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The voltage control is segmented between two gates: the back gate sets the threshold voltage to minimize leakage and reduce the required overdrive, while the front gate applies the necessary overdrive voltage only during brief read/write operations. This segmentation allows fast switching without requiring continuously high overdrive voltage, reducing overall power consumption.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The back gate voltage is adjusted to optimize the threshold voltage, which reduces the magnitude of overdrive voltage needed on the front gate. By changing the threshold voltage parameter through back gate control, the system achieves fast switching with lower power consumption compared to using high overdrive voltage alone.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If a thicker dielectric gate is used to make the transistor resistant to overdrive operation, then transistor reliability improves, but additional manufacturing steps are required and cost increases

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The stress resistance function is segmented from the gate dielectric to a separate back gate structure. Instead of making the front gate dielectric thicker to resist overdrive stress, a thin back gate dielectric is used with an independently controlled back gate that provides the necessary stress compensation. This segmentation allows use of standard thin dielectric processes while achieving the same reliability benefit.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables efficient operation of embedded DRAMs with reduced power consumption and simplified manufacturing by controlling the threshold voltage through the back gate, eliminating the need for overdrive voltage and long channel transistors.

Implementation Method 1

the select transistor has a front gate and a back gate

Methodology Applied
Scientific EffectThreshold voltage control: Electric Field

Data Source

PatentUS9472469B2Back gate in select transistor for eDRAM
Publication Date: 2016.10.18 SOITEC SA
  • US9472469B2 patent drawing
  • US9472469B2 patent drawing
  • US9472469B2 patent drawing

AI summary

This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.