Back-Gate Semiconductor Package Thermal Dissipation
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Solution Overview
Problem
High-performance semiconductor dies generate significant heat due to dense integration of transistors and high operation speeds, necessitating improved heat dissipation in semiconductor packages, particularly for field effect transistors (FETs) on silicon-on-insulator (SOI) substrates, where back-gate transistors are needed to control the channel and reduce leakage current.
Innovation Solution
A thermally enhanced semiconductor package design incorporating a buried oxide layer, epitaxial layers, a gate dielectric, and front- and back-gate structures, along with thermal conductive components and isolation regions, to facilitate effective heat dissipation and independent back-gate bias voltage control, while using thermal conductive materials with high thermal conductivity to enhance heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-performance transistors are densely integrated on semiconductor dies to increase processing power, then productivity and performance are improved, but heat generation increases significantly
Solution Approach 1:
The patent introduces a third dimension by implementing a back-gate structure that accesses the channel from the substrate side, perpendicular to the traditional front-gate control. This dimensional addition allows independent control of the channel without increasing planar footprint, enabling higher transistor density while maintaining thermal performance through enhanced heat dissipation paths via the substrate.
Solution Approach 2:
The patent segments the gate control into two independent parts: front-gate for primary channel control and back-gate for secondary control and threshold adjustment. This segmentation allows optimized control schemes that can reduce leakage current and improve switching efficiency, thereby reducing unnecessary heat generation from leakage while maintaining high integration density.
2Reliability
If back-gate transistors are implemented on SOI substrates to reduce leakage current, then reliability is improved, but thermal dissipation becomes more challenging due to the buried oxide layer
Solution Approach 1:
The patent uses the substrate as a thermal intermediary by implementing the back-gate structure that directly contacts the channel through the substrate. This intermediary approach allows the substrate to serve dual functions: providing mechanical support and electrical control while simultaneously acting as a heat sink to conduct away generated heat, thus resolving the thermal isolation problem caused by the buried oxide layer.
Solution Approach 2:
The patent changes the electrical and thermal parameters of the back-gate structure by adjusting the substrate doping profile and creating localized regions with enhanced carrier concentration. These parameter changes improve the back-gate's ability to control the channel and simultaneously enhance its thermal conduction properties, allowing better heat dissipation while maintaining leakage reduction benefits.
3Temperature
If the first BOX layer is made thinner to improve heat dissipation, then thermal performance is enhanced, but manufacturing precision requirements increase due to potential damage to the thermal conductive component
Solution Approach 1:
The patent applies preliminary thermal treatment to the thermal conductive component before depositing the first BOX layer. This pre-heating or pre-conditioning of the substrate creates a more forgiving interface that accommodates thinner BOX layers without causing thermal shock or mechanical damage during subsequent processing steps, thereby enabling better heat dissipation while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs composite material structures at the interface between the BOX layer and the thermal conductive component, using gradient doping profiles or intermediate buffer layers. This composite approach creates a gradual transition in thermal and mechanical properties, reducing stress concentration and enabling thinner BOX layers to be manufactured with acceptable precision tolerances while maintaining enhanced thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances thermal performance and reduces leakage current by allowing for better heat dissipation and independent back-gate biasing, improving the reliability and efficiency of high-performance semiconductor packages.
Implementation Method 1
a thermal conductive component, which has a thermal conductivity greater than 2.5 w/m·k. Herein, the first BOX layer resides over the thermal conductive component
Data Source
AI summary
The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.