Back Gate and Shielding Bit Line Layout for Stable DRAM Threshold Voltage
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Solution Overview
Problem
The miniaturization of vertical channel transistors in memory devices leads to decreased threshold voltage and increased coupling noise between bit lines, affecting the stability and performance of memory cells.
Innovation Solution
A memory device design that includes a mesh structure connecting back gate lines to a shielding bit line, controlled by a voltage generator to maintain a stable voltage level, thereby stabilizing the threshold voltage of vertical channel transistors and reducing coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical channel transistors are miniaturized to increase integration density, then the storage capacity and integration degree are improved, but the threshold voltage decreases and leakage current increases
Solution Approach 1:
The back gate electrode is configured to be movable or adjustable, allowing dynamic control of the threshold voltage. By applying different voltages to the back gate electrode, the threshold voltage can be tuned to compensate for the effects of miniaturization, thereby maintaining reliable operation while achieving high integration density
Solution Approach 2:
The threshold voltage is controlled by changing the voltage parameter of the back gate electrode. This parameter change allows compensation for the threshold voltage reduction caused by miniaturization, enabling stable operation of vertically integrated transistors
2Productivity
If bit lines are placed closer together to increase integration density, then the storage capacity is improved, but coupling noise between bit lines increases
Solution Approach 1:
A shielding structure is introduced as an intermediary element between adjacent bit lines. This shielding structure acts as a mediator that blocks or reduces the electromagnetic coupling noise between closely spaced bit lines, enabling high-density integration while maintaining signal integrity
Solution Approach 2:
The shielding structure is maintained at a constant voltage potential (equipotential) to minimize voltage differences between adjacent bit lines. By keeping the shielding structure at a fixed potential, electromagnetic interference and coupling noise are reduced, allowing bit lines to be placed closer together
3Ease of operation
If word line voltage is increased to enable selected memory cell operation, then the memory cell activation is improved, but the back gate electrode voltage changes and threshold voltage stability degrades
Solution Approach 1:
The back gate electrode voltage is controlled through a feedback mechanism that monitors and compensates for voltage changes induced by word line switching. When the word line voltage changes to activate a memory cell, the feedback system adjusts the back gate voltage accordingly to maintain stable threshold voltage
Solution Approach 2:
The back gate electrode voltage is preemptively adjusted in opposition to the expected threshold voltage changes caused by word line voltage transitions. By applying a counteracting voltage to the back gate before or during word line switching, the threshold voltage stability is maintained despite large word line voltage swings
Data Source
AI summary
A memory device includes a plurality of memory blocks and a voltage generator. Each of the plurality of memory blocks may include a plurality of word lines extending in a first direction of the memory device, a plurality of back gate lines that are each adjacent to a respective word line of the plurality of word lines, a plurality of bit lines extending in a second direction perpendicular to the first direction, and a shielding bit line arranged between the plurality of bit lines and under the plurality of bit lines. The back gate lines are electrically connected to the shielding bit line. The voltage generator may be configured to drive the shielding bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level.