Back Gate Formation Under SOI Devices Without Wider Isolation Trenches
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Solution Overview
Problem
Current methods for producing rear gates under semiconductor devices on SOI substrates are invasive and limit integration density due to wide insulation trenches and residual dopants incompatible with quantum dot operations.
Innovation Solution
A method involving the formation of insulation trenches around semiconductor devices, with partial etching to selectively remove a sacrificial layer, allowing for precise control of trench dimensions and enabling the formation of conductive rear gates without increasing trench width, thus increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wide insulation trenches are used to form back gates, then back gate fabrication is enabled, but integration density decreases
Solution Approach 1:
The patent introduces a sacrificial layer positioned between adjacent devices that is selectively removed to create isolated etching regions. This segmentation allows narrow insulation trenches to be formed for each device independently, enabling back gate fabrication without requiring wide trenches that would impact neighboring devices. The sacrificial layer acts as a temporary divider that is removed only where needed to create the back gate cavity.
Solution Approach 2:
The sacrificial layer serves as an intermediary element that facilitates the formation of narrow insulation trenches. By temporarily occupying the space between devices and then being selectively removed, it enables the etching process to create precise, narrow trenches without affecting adjacent devices. This intermediary approach allows the system to achieve both narrow trench widths (for high density) and complete back gate formation.
2Ease of manufacture
If front-side ion implantation is used to create conductive back gate, then doping is achieved, but residual dopants contaminate the surface semiconductor layer
Solution Approach 1:
The patent extracts the doping function from the back gate formation process. Instead of using ion implantation to create conductivity in the back gate, the method uses a separate doping process applied only to the surface semiconductor layer's active region. The back gate is formed as a distinct conductive structure beneath the insulation layer, separating the doping operation from the back gate fabrication and preventing residual dopant contamination of the surface layer.
Solution Approach 2:
The patent segments the conductivity creation process into two independent operations: (1) doping of the surface semiconductor layer in the active region, and (2) formation of the conductive back gate structure. This segmentation ensures that dopants are introduced only where needed in the surface layer without being deposited into the back gate region, maintaining surface layer purity while still achieving the desired conductive back gate.
3Quantity of substance
If narrow insulation trenches are used to increase integration density, then device spacing is reduced, but back gate formation becomes difficult
Solution Approach 1:
The patent applies preliminary action by forming the sacrificial layer before creating the insulation trenches. This sacrificial layer pre-defines the exact regions where trenches should be formed and protects adjacent areas. By having this preliminary structure in place, the etching process can confidently create narrow trenches knowing that the sacrificial layer will guide the etching and prevent damage to neighboring devices, thus enabling narrow trench formation without compromising back gate fabrication.
Solution Approach 2:
The sacrificial layer acts as an intermediary that enables narrow trench formation. It provides a physical boundary that allows the etching process to create very narrow trenches with precise control, knowing that the sacrificial material will protect adjacent regions. This intermediary structure makes it feasible to form back gates under narrow trenches that would otherwise be too tight to work with using conventional methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances integration density by allowing for the precise formation of rear gates under semiconductor devices, enabling co-integration of multiple devices without increasing trench width, and maintaining functional insulation between adjacent devices.
Implementation Method 1
selective removal of the sacrificial layer to the semiconductor layer, the support layer and the insulation trenches, so as to form a cavity under the semiconductor device
Implementation Method 2
filling of the cavity with an electrically conductive material so as to form the back grid under the semiconductor device
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
The invention relates to a method for creating a back grid (5) under a semiconductor device (D1) surrounded by insulating trenches (2), comprising: • partial etching of the insulating trenches (2) forming an opening (40b) to the sacrificial layer (11), • selective removal of the sacrificial layer (11) forming a cavity (50) under the device (D1), • filling the cavity (50) with a conductive material to form the back grid (5). Advantageously, the formation of the insulating trenches (2) includes the formation of a sacrificial coating layer (15) at the sides (21) of the trenches, in contact with the sacrificial layer (11), before filling with an insulating material (16), and the partial etching of the trenches (2) includes the selective removal of this sacrificial coating layer (15) to the insulating material (16).