Back-Gate Switching Circuit for Low-Power Neural Product-Sum
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Solution Overview
Problem
The increasing complexity and size of artificial neural networks lead to high power consumption and heat generation, affecting the characteristics of circuit components and making them temperature-sensitive, which is undesirable.
Innovation Solution
A semiconductor device with a hierarchical artificial neural network architecture that includes specific transistor and inverter circuits, along with holding units and switching circuits, optimized to reduce power consumption and temperature sensitivity by managing signal transmission and potential holding efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of circuits corresponding to neurons and synapses increases to scale up the artificial neural network, then the calculation capability and processing power increase, but the power consumption and heat generation increase significantly
Solution Approach 1:
The patent divides the artificial neural network into multiple stages, with each stage containing a limited number of neurons and synapses. This segmentation allows the system to achieve high calculation capability through multi-stage processing while keeping power consumption manageable at each individual stage. The multi-stage architecture processes information sequentially, distributing the computational load across multiple smaller units rather than requiring one large power-consuming unit.
2Productivity
If the number of circuits corresponding to neurons and synapses increases to scale up the artificial neural network, then the calculation capability increases, but the heat generation increases and affects circuit component characteristics
Solution Approach 1:
By dividing the neural network into multiple stages with limited neurons each, the patent distributes heat generation across multiple smaller units rather than concentrating it in one large unit. This segmentation enables better thermal management as each stage generates less heat individually, and the distributed architecture allows for more efficient heat dissipation across the overall system.
Solution Approach 2:
The multi-stage architecture processes information in sequential periods, with each stage processing a portion of the data before passing it to the next stage. This periodic processing approach allows thermal energy to dissipate between processing stages, preventing cumulative heat buildup that would occur with simultaneous processing in a single large unit.
3Productivity
If the number of circuits corresponding to neurons and synapses increases to scale up the artificial neural network, then the calculation capability increases, but the circuit components become more sensitive to ambient temperature variations
Solution Approach 1:
The patent segments the neural network into multiple stages, where each stage contains a manageable number of circuits. This segmentation reduces the overall temperature sensitivity of the system because each individual stage is less sensitive to temperature variations than a single large unit would be. The distributed architecture provides inherent redundancy and stability, making the overall system more reliable despite increased calculation capability.
Data Source
AI summary
A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.