Back Gate Transistor for Oxide Semiconductor Memory Retention
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Solution Overview
Problem
Semiconductor memory devices using oxide semiconductors with wide bandgaps face challenges in retaining data for extended periods without external power, especially due to increased subthreshold values at higher temperatures and short channel effects, which limit the off-state current and data retention.
Innovation Solution
Incorporating back gate transistors in strategic locations within the bit lines of the memory device, such as between the column driver and the bit line, to maintain a constant potential and reduce leakage currents, thereby enhancing data retention even during power interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductors with wide bandgaps are used to reduce off-state current, then data retention is improved, but subthreshold value increases at higher temperatures reducing retention effectiveness
Solution Approach 1:
The patent applies parameter changes by adjusting the potential of the back gate to dynamically control the threshold voltage of the transistor. By changing the back gate potential, the threshold voltage can be optimized for different temperature conditions, thereby maintaining low subthreshold values and effective data retention even at higher temperatures where oxide semiconductor transistors naturally exhibit increased subthreshold values
2Productivity
If transistor size is reduced to increase integration, then device density is improved, but short channel effects increase raising subthreshold value and reducing data retention
Solution Approach 1:
The patent introduces a back gate as an intermediary element that mediates the control of the transistor channel. This back gate acts as a mediator between the control circuit and the channel, enabling independent adjustment of the threshold voltage without being constrained by short channel effects. The back gate potential can be optimized to compensate for the increased subthreshold values caused by reduced transistor dimensions, thereby maintaining data retention while achieving high integration density
3Use of energy by moving object
If gate potential is set to 0 V during power interruption, then power consumption is minimized, but drain current increases reducing data retention
Solution Approach 1:
The patent applies preliminary action by pre-charging or pre-discharging the back gate capacitor before power interruption occurs. This preliminary action sets the back gate potential to an optimal value that ensures the transistor maintains low drain current even when the gate potential drops to 0 V during power interruption. By preparing the back gate state in advance, the system achieves both minimal power consumption and effective data retention during power interruptions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for sufficient data retention across a wide range of temperatures and transistor sizes by minimizing drain current, even when the gate potential is 0 V, effectively increasing the off-state resistance and extending the retention period.
Implementation Method 1
The potential of the back gate of the back gate transistor is lower than the minimum potential of the word line
Implementation Method 2
a transistor formed using an oxide semiconductor with a wide bandgap in the subthreshold region can be roughly estimated from the subthreshold value and the threshold voltage
Data Source
AI summary
An object is to increase the retention characteristics of a memory device formed using a semiconductor with a wide bandgap, such as an oxide semiconductor. A transistor including a back gate (a back gate transistor) is inserted in series at one end of a bit line so that the back gate is constantly at a sufficiently negative potential. The minimum potential of the bit line is set higher than that of a word line. When power is turned off, the bit line is cut off by the back gate transistor, ensuring prevention of outflow of charge accumulated in the bit line. At this time, the potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor (0 V), so that the cell transistor is put in a sufficiently off state; thus, data can be retained.