Vertical Channel Memory Structure With Back-Gate for Dense Arrays
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase integration density and improve electric characteristics while overcoming the limitations of expensive equipment needed for fine pattern formation in two-dimensional or planar devices.
Innovation Solution
A semiconductor memory device design featuring bit lines, active patterns, word lines, back-gate electrodes, and insulating patterns, with specific arrangements and structures that enhance integration density and electric characteristics, including the use of single-crystalline semiconductor materials and vertical channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area constraints
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertical channel transistors. The active pattern extends vertically with a channel length in the vertical direction, enabling higher integration density by utilizing the third dimension while maintaining manufacturability through established fabrication processes adapted for vertical structures.
2Quantity of substance
If pattern fineness is increased to improve integration density, then integration density increases, but process equipment cost increases significantly
Solution Approach 1:
By transitioning to vertical channel transistors, the patent achieves higher integration density without requiring extreme pattern fineness. The vertical orientation allows denser packing of memory cells in the horizontal plane while the channel length is defined by vertical etching depth rather than lateral lithography resolution, reducing dependence on expensive fine-patterning equipment.
Solution Approach 2:
The patent changes the critical dimension from lateral pattern size to vertical etch depth. This parameter transformation allows integration density to be controlled by vertical processing parameters rather than lateral lithography parameters, potentially reducing equipment complexity and cost while achieving higher density.
3Device complexity
If conventional planar structures are used, then device structure is simpler, but electric characteristics such as leakage current and threshold voltage are deteriorated
Solution Approach 1:
The vertical channel transistor structure improves electric characteristics by increasing the effective channel area while maintaining compact footprint. The vertical orientation enables better control of leakage current through the channel and improves threshold voltage control via the gate electrode positioned adjacent to the vertical channel, enhancing reliability without excessive structural complexity.
Data Source
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AI summary
A semiconductor memory device is disclosed. The semiconductor memory device includes a bit line (BL; 161, 163) extending in a first direction, first and second active patterns (AP1, AP2) disposed on the bit line (BL), a back-gate electrode (BG), which is disposed between the first and second active patterns (AP1, AP2) and is extended in a second direction to cross the bit line (BL), a first word line (WL1), which is provided at a side of the first active pattern (AP1) and is extended in the second direction, a second word line (WL2), which is provided at an opposite side of the second active pattern (AP2) and is extended in the second direction, and contact patterns (BC) coupled to the first and second active patterns (AP1, AP2), respectively.