Back-Gate Well Layout for Lower GIDL in High-Voltage Transistors
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Solution Overview
Problem
Subthreshold leakage current and gate-induced drain leakage (GIDL) current are significant contributors to leakage currents in off-state transistors, particularly dominant in high voltage ranges, posing challenges for efficient transistor operation.
Innovation Solution
The transistors share a voltage difference between the voltage levels LDD and LSS, reducing the voltage difference between the drain terminal and back gate terminal, which in turn reduces GIDL currents by configuring the transistors such that the drain terminal of one transistor and the back gate terminal of another have smaller voltage differences, thereby minimizing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors operate in high voltage range, then power handling capability is improved, but GIDL current increases
Solution Approach 1:
The patent divides the transistor structure into multiple wells (first well, second well, third well) with separate back gate terminals. This segmentation allows independent voltage control of each well, enabling the back gate voltage to be optimized to reduce GIDL current while maintaining high voltage operation capability.
Solution Approach 2:
The patent changes the voltage parameter by applying a back gate voltage that is different from both the first voltage (at drain terminal) and second voltage (at source terminal). This parameter adjustment reduces the electric field intensity at the drain-end junction, thereby reducing GIDL current while maintaining power handling capability.
2Power
If drain terminal and back gate terminal have large voltage difference, then transistor can handle high voltage, but leakage current increases
Solution Approach 1:
The back gate terminal acts as an intermediary between the drain terminal and source terminal. By applying an intermediate voltage level to the back gate that is between the first voltage and second voltage, the patent reduces the electric field intensity at the drain-end junction, thereby reducing GIDL current while maintaining voltage handling capability.
Solution Approach 2:
The patent dynamically adjusts the back gate voltage to be different from both the first voltage and second voltage, creating a dynamic voltage distribution that optimizes both voltage handling capability and reduces leakage current. This dynamic voltage control allows the transistor to adapt to different operating conditions.
Data Source
AI summary
A semiconductor device includes a first well and a second well. The first well is configured to operate as a back gate terminal of a first transistor. The second well is separated from the first well, and is configured to operate as a back gate terminal of a second transistor. Each of a first source/drain terminal of the second transistor, and a first source/drain terminal of the first transistor and the back gate terminal of the first transistor are coupled to each other.