Back-Gated Fe-FET Memory Structure for Low-Voltage Retention
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Solution Overview
Problem
Current flash memory technologies face challenges in balancing operation voltage and retention time due to the incorporation of thin tunneling layers, leading to storage information loss and increased leakage current, while ferroelectric field-effect transistors (Fe-FETs) require complex configurations and consume more area for differential sensing.
Innovation Solution
A novel embedded flash transistor technology using a back-gated thin film transistor (TFT) configuration with a ferroelectric fin field effect transistor (Fe-FET) and a triple dielectric structure, allowing for efficient data storage and reduced area consumption by integrating ferroelectric layers in the gate dielectric stack, enabling complementary write operations and differential reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If thin tunneling layers are used in flash memory, then operation voltage is reduced, but retention time deteriorates and leakage current increases
Solution Approach 1:
The patent merges the tunneling layer and charge storage function into a single integrated structure by forming a discontinuous metal oxide layer within the gate dielectric stack. This eliminates the need for separate thin tunneling layers while maintaining low operation voltage and ensuring adequate retention time through the ferroelectric material's inherent charge storage capability.
Solution Approach 2:
The patent employs a composite gate dielectric structure consisting of a ferroelectric material layer (e.g., hafnium zirconium oxide) combined with a discontinuous metal oxide layer. This composite structure provides both the low operation voltage characteristics of thin tunneling layers and the retention properties of thicker dielectric structures, while the metal oxide layer specifically addresses leakage current reduction.
2Area of stationary object
If ferroelectric layers are integrated in gate dielectric stack, then area requirements are reduced, but device complexity increases
Solution Approach 1:
The gate dielectric stack is designed to perform multiple functions simultaneously: the ferroelectric material layer provides non-volatile memory storage, the discontinuous metal oxide layer serves as a tunneling barrier and charge storage medium, and the overall structure enables both read and write operations. This multi-functionality consolidates what would otherwise require separate components into a single integrated structure, reducing area while managing complexity through functional integration.
Solution Approach 2:
The gate dielectric stack is segmented into distinct functional layers: a bottom dielectric layer, a ferroelectric material layer, and a discontinuous metal oxide layer. This segmentation allows each layer to be optimized for its specific function while maintaining a relatively simple overall structure that can be fabricated using standard semiconductor processing techniques, thus reducing area without excessive complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data retention and reduces area requirements, achieving counter-clockwise hysteresis in current versus voltage curves with nearly ideal sub-threshold slopes and improved memory window, enabling efficient and compact non-volatile memory integration.
Implementation Method 1
a ferroelectric structure (108) over and electrically connected with the gate structure
Implementation Method 2
a tunneling layer (104) sandwiched there-between
Implementation Method 3
achieving counter-clockwise hysteresis in current versus voltage curves
Data Source
AI summary
A memory device includes a gate structure, a ferroelectric structure over and electrically connected with the gate structure, a channel structure over the ferroelectric structure, and a plurality of contact structures over the channel structure. The gate structure includes a first gate as a back gate, a second gate as a floating gate, and a tunneling layer sandwiched there-between. The plurality of contact structures is laterally spaced apart with each other by a predetermined distance. In some embodiments, the sidewalls of the first gate are aligned with sidewalls of the plurality of contact structures.