Back-Side DRAM Capacitor Transfer for Semiconductor Logic Integration
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Solution Overview
Problem
The increasing complexity and power dissipation in semiconductor integrated circuits (ICs) due to scaling down processes lead to challenges in maintaining efficient manufacturing and performance, particularly in addressing high resistance and capacitance requirements between logic and DRAM regions on ICs.
Innovation Solution
A method involving the transfer of a stacked DRAM capacitor to the wafer back-side, eliminating the need for additional interconnect structures over the logic region, which allows for improved capacitance and reduced resistance by enabling wider bit-line/word-line metal widths and deeper capacitor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but power dissipation increases
Solution Approach 1:
The patent moves the capacitor structure from the front side to the back side of the wafer, utilizing the third dimension (depth/vertical space) and the back side surface area. This dimensional change allows capacitors to be positioned away from the logic region, reducing their impact on front-side interconnect complexity while maintaining high functional density.
Solution Approach 2:
The wafer is divided into front side (logic region) and back side (capacitor region), separating the functions of logic circuits and storage capacitors. This segmentation allows each region to be optimized independently, with the logic region focusing on low power dissipation and the back side accommodating high-capacitance structures.
2Reliability
If additional interconnect structures are added over logic region to compensate height difference, then connection between logic and DRAM regions is achieved, but resistance increases and functional density decreases
Solution Approach 1:
Instead of adding interconnect structures over the logic region to bridge height differences, the patent inverts the approach by placing capacitors on the back side of the wafer. This eliminates the need for additional front-side interconnect layers, reducing resistance and simplifying the interconnect structure while maintaining reliable connections.
3Ease of manufacture
If capacitor structures are placed on front side to maintain height alignment, then manufacturing simplicity is maintained, but capacitance is limited and resistance increases
Solution Approach 1:
The patent exploits the back side of the wafer as an additional manufacturing dimension, allowing capacitor structures to be formed separately from the front-side logic region. This enables the formation of deeper, higher-capacitance structures without complicating the front-side manufacturing process, as capacitors can be fabricated in a separate back-side processing sequence.
Data Source
AI summary
A method includes forming a transistor on a front-side of a substrate, the transistor comprising a channel region, a gate structure surrounding the channel region, and source/drain regions on opposite sides of the gate structure; forming a front-side contact on a first one of the source/drain regions of the transistor, forming a back-side contact on a second one of the source/drain regions of the transistor; forming a back-side capacitor on the back-side contact.