Back-Side Component Mounting for Compact Semiconductor Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging methods often increase the package form factor when incorporating additional components, such as passive or active components, which can be undesirable for microchip packaging.
Innovation Solution
A semiconductor assembly is created by mounting electronic components on the back side of a semiconductor die using a dielectric material or metallization layer, allowing for the incorporation of components without increasing the package form factor, through the use of component pads and signal traces, and solder connections with a solder non-wettable area provided by the dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional components are packaged along the periphery of the die, then the functionality of the semiconductor package is improved, but the package form factor increases
Solution Approach 1:
The patent applies dimensionality change by moving component placement from the traditional periphery (2D plane) to the back side of the die (utilizing the third dimension/depth). This allows components to be mounted on the back surface of the semiconductor die rather than extending the package footprint, thereby maintaining a compact form factor while achieving enhanced functionality through integrated passive and active components.
2Productivity
If multiple microchips are accommodated in a single package, then the production cost is reduced, but the device complexity increases
Solution Approach 1:
The patent merges multiple functional elements into a single integrated package structure. Multiple microchips, passive components, and interconnection structures are combined within one package housing, with components mounted on the back side of the die and interconnected through metallization layers and dielectric materials. This consolidation achieves cost reduction through shared packaging infrastructure while managing complexity through systematic integration architecture.
Solution Approach 2:
The patent implements a nested structure where multiple chips and components are housed within a single package container. The back side of the semiconductor die serves as a substrate for mounting additional components, creating a nested arrangement where smaller functional units are integrated within the larger package structure. This nesting approach enables multiple chips to coexist in a compact configuration, reducing overall production costs while organizing complexity through hierarchical structuring.
Data Source
AI summary
One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.