Back Side Deep Trench Isolation for CMOS Image Sensor Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors face issues such as high dark current, white pixel defects, and reduced dynamic range due to floating diffusion junction leakage, especially in low conversion gain scenarios, which affect image quality and production costs.
Innovation Solution
The implementation of a back side deep trench isolation structure around the perimeter of the pixel transistor region and between photodiode regions, combined with front side shallow trench isolation, to reduce diffusion leakage and crosstalk, thereby isolating the transistor channel region and enhancing the signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If device geometries are scaled down to achieve higher integration density and resolution, then device integration density and resolution are improved, but floating diffusion junction leakage increases causing high dark current and white pixel defects
Solution Approach 1:
A back side deep trench isolation structure is introduced as an intermediary element between the pixel transistor region and the floating diffusion region. This isolation structure physically separates the two regions, preventing direct leakage current flow while allowing the device geometries to be scaled down for higher integration density. The trench isolation acts as a mediator that blocks the harmful leakage path without interfering with the miniaturization benefits.
2Manufacturing precision
If pixel size and pitch are reduced to achieve higher resolution, then resolution is improved, but crosstalk and diagonal flare increase due to asymmetric layouts
Solution Approach 1:
The pixel structure is segmented into distinct regions separated by deep trench isolation structures. The back side deep trench isolation divides the pixel transistor region from the floating diffusion region, creating electrical isolation that prevents crosstalk between adjacent pixels. This segmentation allows each pixel to be miniaturized while maintaining sufficient isolation to prevent unwanted signal interference and diagonal flare effects.
3Object-generated harmful factors
If deep trench isolation structure is added to reduce leakage current, then floating diffusion junction leakage is reduced, but device complexity and fabrication steps increase
Solution Approach 1:
The back side deep trench isolation structure is merged with the existing front side shallow trench isolation to form a complete isolation system. By combining these two isolation approaches at different depths and orientations, the patent achieves comprehensive leakage current suppression without requiring entirely new complex structures. The integration of back side and front side isolation leverages existing fabrication capabilities while effectively reducing leakage current at the floating diffusion region.
Data Source
AI summary
Examples of the disclosed subject matter propose disposing deep trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. In some example embodiments, the deep trench isolation structure extends into the semiconductor substrate from the back side of the semiconductor substrate and abuts against or contacts the bottom of shallow trench isolation structure disposed in the front side of the semiconductor substrate. Together, the trench isolating structure isolates the transistor channel of the pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, such as a floating P-doped well region (P-well), containing a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.