Back-Side DRAM Capacitor Fabrication for Scaling Bottlenecks
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Solution Overview
Problem
The scaling of dynamic random access memory (DRAM) technologies is constrained by the difficulty in fabricating capacitors with sufficient geometric volume, as conventional processing methods struggle to increase capacitance in memory cells, limiting device scaling and requiring high etch aspect ratios and conformal dielectric layer deposition in deep trench structures.
Innovation Solution
The method involves forming capacitors on the back side of a substrate, allowing for increased capacitance without the need for complex front-side metal routing, using a process that includes thinning the substrate to expose the back side for etching and deposition of capacitive structures, which can include conductive regions and dielectric materials to enhance capacitance without extending above the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trench structures are used to accommodate capacitors, then capacitance can be increased, but etch aspect ratios become very high and conformal dielectric layer deposition becomes required
Solution Approach 1:
The patent inverts the conventional capacitor placement approach by forming capacitors on the back side of the substrate rather than in deep trenches on the front side. This inversion eliminates the need for high aspect ratio etching while maintaining increased capacitance through alternative geometric configurations.
Solution Approach 2:
The patent transitions from vertical capacitor structures (requiring deep trenches) to horizontal capacitor structures formed on the back side of the substrate. This dimensional change allows capacitance increase without requiring high etch aspect ratios, as capacitors are formed in a planar configuration rather than deep vertical trenches.
2Quantity of substance
If capacitors are placed above the substrate, then capacitance can be provided, but device scaling is limited due to interference with metal layer routing
Solution Approach 1:
The patent inverts the conventional capacitor placement by moving capacitors from the front side (above substrate) to the back side of the substrate. This inversion removes the conflict between capacitor structures and metal layer routing, enabling continued device scaling without interference.
3Ease of manufacture
If conventional front-side processing is used, then fabrication can proceed, but capacitor geometric volume is insufficient for scaling
Solution Approach 1:
The patent utilizes the back side of the substrate as an additional dimensional space for capacitor formation. This approach increases capacitor geometric volume without complicating the fabrication process, as standard thinning and front-side processing techniques are combined with back-side capacitor formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of memory cells with increased capacitance, mitigating the limitations of conventional DRAM scaling and allowing for larger capacitor structures, thereby improving memory cell performance without interfering with metal layer routing.
Implementation Method 1
capacitor coupled to accumulate charge based on activation of a channel between the first doped region and the second doped region
Data Source
AI summary
Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.