Back-Side Integrated Circuitry for Semiconductor Imagers
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Solution Overview
Problem
Conventional imager fabrication methods face challenges in minimizing peripheral dimensions due to densely packed conductive lines causing cross-talk and capacitance issues, as well as the 'snowplow' effect from color filter arrays and the need for bond wires, which occupy valuable real estate and increase device thickness and cost.
Innovation Solution
Fabricating contact openings, contact plugs, and conductive lines on the back side of the substrate, allowing for reduced peripheral dimensions and integrated circuitry, thereby minimizing the overall size and thickness of the imager while reducing undesirable electrical effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conductive lines are densely packed into peripheral areas to maximize image sensing element area, then image sensing area is improved, but cross-talk and capacitance issues worsen
Solution Approach 1:
The patent moves conductive lines from the two-dimensional peripheral plane to the third dimension by routing them through the thickness of the substrate (via-holes) and along the back surface. This dimensional transition allows conductive lines to access peripheral areas without occupying valuable peripheral real estate on the active surface, thereby maintaining high image sensing area while eliminating cross-talk and capacitance issues associated with dense planar routing.
Solution Approach 2:
The patent segments the conductive interconnect path into multiple sections: contact openings through the substrate, via-holes for vertical routing, and conductive lines on the back surface. This segmentation allows the conductive pathways to be distributed in three-dimensional space rather than confined to a single plane, reducing electromagnetic interference while maintaining electrical connectivity.
2Reliability
If through-wafer interconnects are used to provide contacts, then contact connectivity is improved, but manufacturing complexity and cost worsen
Solution Approach 1:
The patent extracts the most complex portion of the through-wafer interconnect process by forming contact openings only to a partial depth (stopping before completely through the substrate) and then completing the interconnect using simpler back-surface processing. This extraction of the difficult through-hole drilling step reduces manufacturing complexity while maintaining full connectivity, as the remaining substrate thickness is accessed via easier-to-form via-holes from the back surface.
3Reliability
If bond wires are used to connect imagers to carriers, then electrical connection is improved, but device footprint and carrier real estate worsen
Solution Approach 1:
The patent transitions bond pad connections from lateral extension on the carrier plane to vertical integration through the substrate. By providing contact openings that extend through the substrate and forming conductive lines on the back surface, the patent enables direct vertical connections to the carrier, eliminating the need for lateral bond wire extensions and reducing the footprint on the carrier.
4Reliability
If color filter array materials are applied over thinned dielectric regions, then color filtering is improved, but peripheral dead zones increase
Solution Approach 1:
The patent inverts the conventional approach by applying the color filter array material over the thinned dielectric regions in the periphery rather than avoiding these areas. This inversion allows the CFA materials to be uniformly applied across the entire surface, including peripheral regions, eliminating the need for dead zones while maintaining proper color filtering through the thinned areas.
Data Source
AI summary
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings. At least one laterally extending conductive element may be electrically connected to a first transistor or capacitor and may extend laterally underneath a second, different transistor or capacitor to which the laterally extending conductive element is not electrically connected.