Back-Side Memory Array in 3D Integrated Circuit
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Solution Overview
Problem
In three-dimensional integrated circuits, existing designs face challenges in efficiently integrating embedded memory due to limitations in routing electrical signals between the control circuit and memory array, leading to increased complexity and manufacturing difficulties.
Innovation Solution
The implementation of a memory circuit in three-dimensional integrated circuits where the memory array is located in back-side metal layers, allowing for shorter and simpler signal routing, with the control circuit in the logic layer, and using thicker back-side metal layers to improve performance and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory array is placed in front-side metal layers above the logic transistors, then the memory can be integrated on the same IC die, but the signal routing becomes complex and manufacturing becomes difficult
Solution Approach 1:
The patent applies dimensionality change by moving the memory array from the front-side metal layers to the back-side metal layers of the IC die. This spatial reconfiguration places the memory array in a different dimensional plane relative to the logic transistors, allowing for simplified signal routing through thicker metal layers while maintaining integration on the same die. The back-side placement enables more direct vertical connections and reduces the complexity of lateral routing paths.
Solution Approach 2:
The patent segments the IC die into distinct functional layers: the front side contains logic transistors and control circuits, while the back side contains the memory array. This segmentation allows each side to be optimized independently - the front side for control logic and the back side for memory storage - thereby simplifying the overall signal routing architecture and manufacturing process.
2Area of stationary object
If thinner metal layers are used for memory array, then the IC die size can be reduced, but the signal routing performance deteriorates
Solution Approach 1:
The patent applies local quality by using thicker metal layers specifically for the memory array region on the back side of the IC die, while the front side maintains its standard metal layer thickness for logic circuits. This localized adjustment of metal layer thickness optimizes signal routing performance for memory operations without unnecessarily increasing the overall IC die size, as the thicker layers are confined to the memory array area.
3Device complexity
If the memory array is placed farther from the logic layer, then the signal routing becomes simpler, but the placement flexibility is reduced
Solution Approach 1:
The patent resolves this contradiction by utilizing the back-side dimension of the IC die for memory array placement. This creates optimal separation between the logic layer on the front side and the memory array on the back side, simplifying signal routing while maintaining placement flexibility. The vertical separation in the third dimension (depth) allows for independent optimization of both routing simplicity and placement adaptability.
Data Source
AI summary
Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.