Back-Side Memory Architecture for MRAM Footprint Reduction
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Solution Overview
Problem
Conventional MRAM device fabrication techniques face challenges due to MTJ height constraints and require exotic, non-CMOS compatible materials, leading to increased power consumption and limited footprint reduction.
Innovation Solution
A back-side memory architecture is implemented, where a vertical-type field effect transistor (VTFET) with a buried insulator layer and offset memory storage element is formed on opposite sides of a semiconductor wafer, allowing for a reduced footprint and overcoming MTJ height constraints by passing a back-side bit line along the edge of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional MRAM device fabrication techniques are used, then MTJ height constraints are encountered, but this leads to increased power consumption and limited footprint reduction
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical integration by placing the memory storage element (MTJ) on the back side of the wafer and routing control signals through the front side. This vertical stacking approach reduces the planar footprint while managing power consumption through optimized signal routing paths that traverse the wafer thickness dimension.
Solution Approach 2:
The patent inverts the conventional MRAM architecture by positioning the memory storage element on the back side of the wafer rather than the front side. This inversion allows the bit line to be routed along the edge of the memory array on the front side, reducing the footprint required for signal routing while maintaining electrical connectivity to the MTJ.
2Area of stationary object
If conventional MRAM device fabrication techniques are used, then MTJ height constraints are encountered, but this leads to increased device complexity
Solution Approach 1:
The patent utilizes vertical stacking and three-dimensional integration to reduce planar footprint. By routing the bit line through the front side of the wafer and placing the MTJ on the back side, the design achieves compact footprint while managing fabrication complexity through systematic layer-by-layer construction and self-aligned processing techniques.
Solution Approach 2:
The patent divides the device into distinct functional regions: the memory array on the back side, the control circuitry on the front side, and interconnect structures traversing the wafer thickness. This segmentation allows independent optimization of each region's fabrication process, reducing overall device complexity despite the three-dimensional architecture.
3Area of stationary object
If MTJ height constraints are imposed, then fabrication is limited, but this prevents footprint reduction
Solution Approach 1:
The patent resolves the MTJ height constraint by utilizing the vertical dimension to route signals through the front side of the wafer. The bit line is positioned to traverse the wafer thickness, allowing the MTJ to be placed on the back side at an optimized height without compromising signal delivery. This three-dimensional routing approach enables footprint reduction while maintaining fabrication feasibility.
Solution Approach 2:
By inverting the conventional architecture and placing the MTJ on the back side, the patent eliminates the need to conform to traditional MTJ height constraints on the front side. The bit line routing through the front side provides flexibility in MTJ positioning, enabling footprint reduction without sacrificing manufacturing ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of MRAM devices with a reduced footprint and improved power efficiency by overcoming MTJ height constraints and allowing for a more compact design without the need for constant charge refreshing.
Implementation Method 1
The magnetic storage elements are formed from two ferromagnetic plates, each of which can hold a magnetization. The two ferromagnetic plates are separated from each other by a thin insulating layer to define a magnetic tunnel junction (MTJ). One of the two ferromagnetic plates is a permanent magnet set to a particular magnetization direction, while the other ferromagnetic plate has a magnetization direction that can be changed to match that of an external field or that can be changed using an applied current to store data.
Data Source
AI summary
A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.