Back-Side Nanoribbon Removal for Transistor Uniformity
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Solution Overview
Problem
The challenge in fabricating nanoribbon transistors is the difficulty in achieving uniformity in geometry and electrical characteristics due to width-dependent process differences, leading to issues with yield and performance for both high-performance and low-power applications.
Innovation Solution
The implementation of back-side nanoribbon removal techniques, which involve forming stacks of nanoribbons from one side and then removing one or more nanoribbons from the opposite side, allowing for the fabrication of transistors with varying nanoribbon widths and numbers, thereby addressing the width-dependent process challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form nanoribbon stacks, then nanoribbon transistors can be fabricated, but uniformity in geometry and electrical characteristics deteriorates due to width-dependent process differences
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming stacks of nanoribbons from a first side, flipping the substrate, and selectively removing nanoribbons from the second side. This segmentation allows independent optimization of each stage, achieving uniformity in the remaining nanoribbons while managing process complexity through systematic division of steps.
Solution Approach 2:
The patent applies inversion by flipping the substrate to access the back side for selective nanoribbon removal. This reverse approach allows precise control over which nanoribbons remain in the stack, enabling uniform geometry and electrical characteristics by eliminating width-dependent process variations that occur in conventional single-side fabrication.
2Adaptability or versatility
If nanoribbon stacks are formed with fixed number and width, then fabrication process is simplified, but adaptability for both high-performance and low-power applications is reduced
Solution Approach 1:
The patent implements local quality by enabling different nanoribbon stacks to have different numbers and widths of nanoribbons based on specific application requirements. High-performance applications can utilize stacks with more nanoribbons for higher current drive, while low-power applications can use stacks with fewer nanoribbons, all fabricated through the same selective removal process.
Solution Approach 2:
The fabrication process becomes dynamic and adjustable through selective nanoribbon removal. Instead of fixing the nanoribbon configuration upfront, the process allows flexible adjustment of the number and width of nanoribbons in each stack by controlling which nanoribbons are removed from the back side, enabling adaptation to different performance requirements.
3Manufacturing precision
If width-dependent process differences are addressed by adjusting fabrication parameters, then uniformity improves, but manufacturing time and complexity increase
Solution Approach 1:
The patent applies preliminary action by forming complete stacks of nanoribbons with uniform dimensions from the first side before any selective removal occurs. This preliminary uniform formation eliminates width-dependent process differences at the source, and the subsequent flipping and selective removal efficiently achieves final uniformity without requiring time-consuming parameter adjustments during fabrication.
Data Source
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AI summary
Fabrication methods for integrated circuit (IC) structures and devices involving back-side nanoribbon removal are described herein. In one example, back-side nanoribbon removal involves providing stacks of nanoribbons from a first side of an IC structure, followed by removing one or more of the nanoribbons from a second side that is opposite the first side. In one example, an IC structure fabricated with back-side nanoribbon removal techniques may include a first stack of nanoribbons over a support and a second stack of nanoribbons over the support, where the number of nanoribbons in the first stack is less than in the second stack. A first transistor includes first channel regions in the nanoribbons of the first stack and a second transistor includes second channel regions in the nanoribbons of the second stack. Therefore, in one such example, the first transistor has channel regions in fewer nanoribbons than the second transistor.