Back-Side Power Distribution Network for Silicon Interconnect Fabric
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Solution Overview
Problem
Power distribution in silicon interconnect fabrics (Si-IF) is challenging due to high resistance and power dissipation issues, which are exacerbated by the constraints of silicon processing techniques and the need for efficient voltage delivery across large wafer-scale integration platforms.
Innovation Solution
A power distribution network (PDN) is implemented using large square-shaped stubs on the back side of the Si-IF substrate with through-wafer vias (TWVs) for power delivery to the front side, incorporating liquid cooling channels for heat extraction and supporting multiple voltage domains, thereby reducing voltage drop and power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is delivered through traditional PCB-like routes in Si-IF, then power distribution can be implemented using conventional methods, but voltage drop and power dissipation become excessive due to high resistance in the interconnect fabric
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the back side of the Si-IF substrate rather than through the front side interconnect fabric. This inversion allows power to bypass the high-resistance routing layers, significantly reducing voltage drop and power dissipation while maintaining reliable power delivery to the dies.
Solution Approach 2:
The patent transitions from two-dimensional planar power distribution on the front side to three-dimensional power delivery through the substrate thickness. By using through-substrate vias and back-side power stubs, power is delivered in the vertical dimension, avoiding the resistance accumulation inherent in extended lateral routing paths.
2Productivity
If large current is routed through fine pitch vertical pillars, then high density interconnections are achieved, but voltage drop increases due to the resistance of the pillars
Solution Approach 1:
The patent segments the power delivery path into multiple parallel conductive paths using arrays of through-substrate vias and power stubs. This segmentation distributes the total current across many individual pillars, reducing the current density and voltage drop in each pillar while maintaining high interconnection density.
Solution Approach 2:
The patent introduces back-side power stubs as intermediary structures that receive power before it enters the vertical pillars. These stubs act as current amplifiers and distribution points, reducing the burden on individual pillars and minimizing voltage drop across the interconnect fabric.
3Adaptability or versatility
If complex power converters are placed on the front side of Si-IF, then multiple voltage domains can be supported, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts complex power conversion functionality from the front side Si-IF and relocates it to external power management integrated circuits (PMICs). This extraction simplifies the Si-IF front side by removing unnecessary complexity while maintaining the ability to support multiple voltage domains through the back-side power delivery infrastructure.
4Ease of manufacture
If conventional power distribution methods are used in Si-IF, then implementation is straightforward, but heat extraction becomes difficult due to the wafer-scale integration density
Solution Approach 1:
The patent makes the power distribution network multi-functional by enabling it to serve both power delivery and heat extraction purposes. The same conductive structures (back-side stubs, through-substrate vias, and front-side ground planes) that distribute power also function as thermal conduction paths, efficiently removing heat from the high-density die integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed PDN achieves a low voltage drop of about 298 μV and dissipates approximately 248 mW, with low current density in TWVs, effectively addressing the power distribution challenges in Si-IF platforms while supporting multiple voltage domains and omitting complex power converters on the front side.
Implementation Method 1
a plurality of conductive posts connected to the back side patterned metal layer
Implementation Method 2
liquid cooling channels embedded within the stubs
Implementation Method 3
a plurality of conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer
Data Source
AI summary
A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.