Back-Side Power Rail Reduces Cell Capacitance in 3nm Transistors
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Solution Overview
Problem
Current semiconductor transistor devices face challenges with complex metal layer routing in the back-end-of-line (BEOL) process as the technology scales down beyond 3 nm, leading to increased mask requirements and voltage drop issues due to thinner metal wires.
Innovation Solution
The implementation of a back-side power rail in semiconductor transistor devices, which relocates the power rail from the front-side to the back-side, reducing metal layer routing complexity, minimizing the number of masks needed, and enhancing voltage drop performance by enlarging the power rail area and active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If metal layer routing is performed in the front-side BEOL process, then power delivery is achieved, but routing complexity and mask requirements increase significantly
Solution Approach 1:
The patent moves the power rail from the front-side metal layers to the back-side substrate, utilizing the third dimension (substrate depth) to resolve the routing complexity. This dimensional shift allows power delivery without interfering with front-side signal routing, eliminating the need for additional masks and simplifying the BEOL process.
Solution Approach 2:
Instead of routing power through the conventional front-side metal layers, the patent inverts the approach by placing the power rail on the back-side of the substrate. This inversion simplifies the front-side routing while maintaining effective power delivery to the device.
2Productivity
If metal wires are made thinner to accommodate scaling, then device density increases, but voltage drop performance deteriorates
Solution Approach 1:
The patent addresses the voltage drop issue by moving the power rail to the back-side substrate, creating a low-impedance power delivery path that does not rely on thin front-side metal wires. This dimensional change allows for larger effective power rail area while maintaining high device density on the front-side.
Solution Approach 2:
The back-side power rail is formed during the substrate preparation stage, before the front-side device fabrication. This preliminary action establishes a robust power delivery infrastructure that supports subsequent high-density device formation without compromising voltage drop performance.
3Reliability
If power rail area is enlarged to reduce IR drop, then voltage delivery improves, but device area increases
Solution Approach 1:
The patent resolves this area trade-off by placing the enlarged power rail on the back-side substrate, utilizing the unused substrate area beneath the device. This allows for a large effective power rail area that reduces IR drop without increasing the device footprint on the front-side active area.
Data Source
AI summary
A semiconductor transistor device including a channel structure, gate structure, a first source/drain structure, a second source/drain structure, and a back-side source/drain contact. The gate structure overlies the channel structure. The first source/drain structure and the second source/drain structure are disposed on opposite endings of the channel structure. The back-side source/drain contact is disposed under the first source/drain structure. A line lies across the gate structure and the first source/drain structure. The line is parallel to an upper surface of the gate structure.