Back-Side Power Rail Integration in Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components without increasing parasitic capacitance and improving transistor performance, particularly in forming functional circuits without unwanted contacts to source/drain regions.
Innovation Solution
The solution involves forming nanostructure field effect transistors (nano-FETs) with dedicated power rails at the back-side of the device layer, avoiding contacts to the front-sides of source/drain regions, which allows for increased performance and additional interconnect routing by freeing up space and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional FET structures with front-side contacts to source/drain regions are used, then interconnect routing is simplified, but parasitic capacitance increases and integration density decreases
Solution Approach 1:
The patent moves the power delivery function from the front-side (2D plane) to the back-side of the device layer, utilizing the third dimension (vertical stacking). By forming power rails on the back-side that extend upward to contact source/drain regions, the invention frees front-side space for signal routing while maintaining power delivery functionality, thereby reducing parasitic capacitance without significantly increasing overall routing complexity.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent segments the power delivery function from the signal routing function by placing power rails on the back-side and signal interconnects on the front-side. This segmentation allows independent optimization of each function, enabling tighter spacing and higher integration density without compromising the precision requirements of lithography processes, as each layer can be optimized separately.
3Reliability
If front-side space is used for both power delivery and signal routing, then routing is simplified, but transistor performance decreases due to increased parasitic capacitance
Solution Approach 1:
The patent utilizes the vertical dimension by extending power rails from the back-side upward to contact source/drain regions, thereby separating power delivery (back-side) from signal routing (front-side). This dimensional separation reduces parasitic capacitance between power and signal lines, improving transistor performance while the multi-layer structure manages the increased device complexity.
Data Source
AI summary
In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.