Back Side Redistribution Conductors for Thinned Substrates
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Solution Overview
Problem
Conventional metal-filled through interconnects in semiconductor fabrication require multiple photopatterning steps and both front and back side processing, leading to increased costs and vulnerability of radiation-sensitive integrated circuits during fabrication, especially when handling smaller sizes and thinned semiconductor substrates.
Innovation Solution
A wafer-level fabrication method that forms through interconnects and back side redistribution conductors using a single metal deposition step with electroless plating, eliminating the need for separate photo patterning and protecting the circuit side during processing with a carrier, while allowing for thinned semiconductor substrates and reduced processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal filled through interconnects are used with multiple photopatterning steps and both front and back side processing, then through interconnects can be formed, but fabrication costs increase and integrated circuits become vulnerable to damage
Solution Approach 1:
The patent inverts the conventional fabrication sequence by forming through interconnects and back side redistribution conductors simultaneously from the back side of the substrate, rather than processing front and back sides separately. This inversion eliminates the need for multiple photopatterning steps and protects the front side circuits during back side processing, directly resolving the contradiction between reliability and device complexity
Solution Approach 2:
The patent merges the formation of through interconnects and back side redistribution conductors into a single fabrication process. By depositing conductive material through the substrate and simultaneously forming both structures, the method reduces the number of separate processing steps while maintaining both functions, thereby reducing fabrication complexity without compromising reliability
2Ease of manufacture
If multiple photopatterning steps are used to form through interconnects, then interconnects can be fabricated, but fabrication costs increase
Solution Approach 1:
The patent applies preliminary action by forming the back side redistribution conductor pattern first on the back side of the substrate before forming the through interconnects. This preliminary patterning allows subsequent metal deposition to simultaneously create both structures in one step, eliminating the need for multiple photopatterning steps and reducing fabrication time while maintaining ease of manufacture
Solution Approach 2:
The patent achieves continuity of useful action by maintaining an uninterrupted deposition process that forms both through interconnects and back side redistribution conductors in a single continuous step. This eliminates idle time between separate patterning and deposition operations, reducing total fabrication time while keeping the manufacturing process simple and continuous
3Volume of moving object
If thinned semiconductor substrates are used, then chip scale packages are achieved, but handling and fabrication become more difficult
Solution Approach 1:
The patent inverts the processing approach by working from the back side of the thinned substrate to form through interconnects, rather than processing from the front side. This inversion allows thinned substrates to be handled more easily since the fragile front side with integrated circuits remains protected, and the back side can be processed without requiring thick substrate support, thus achieving chip scale packages while maintaining ease of manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces fabrication costs and minimizes damage to integrated circuits by simplifying the process, maintaining high electrical conductivity and low parasitic capacitance, and enabling efficient handling of thinned substrates with improved performance characteristics.
Implementation Method 1
A wafer-level fabrication method that forms through interconnects and back side redistribution conductors using a single metal deposition step with electroless plating
Data Source
AI summary
A system includes a supporting substrate and at least one semiconductor substrate. The semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality of through interconnects in the substrate, and redistribution conductors on the back side of the substrate. Each through interconnect includes a via aligned with a substrate contact, and a conductive layer at least partially lining the via in physical and electrical contact with the substrate contact. Each redistribution conductor is formed by a portion of the conductive layer.