Back Surface Capacitor Integrated Circuit Reducing Parasitic Inductance
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Solution Overview
Problem
Existing integrated circuits face challenges in effectively decoupling high-frequency noise due to parasitic inductance issues, particularly in output circuits where the distance between decoupling capacitors and load circuits creates significant parasitic inductance, limiting the effectiveness of decoupling capacitors.
Innovation Solution
The integration of through-semiconductor vias (TSVs) in integrated circuits allows for the placement of decoupling capacitors close to transistors, reducing parasitic inductance and enabling a low impedance path across an extended frequency range by positioning metal plates on the back surface of the semiconductor substrate, separated by a dielectric layer, and connecting them to transistors on the front surface using patterned metal networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large decoupling capacitance is used to reduce impedance, then the decoupling effectiveness is improved, but the capacitor size and wire length increase, producing parasitic inductance that limits usefulness
Solution Approach 1:
The patent moves the decoupling capacitor from the traditional planar layout on the same layer to a three-dimensional configuration using through-semiconductor vias. The capacitor is formed with metal plates on opposite sides of the semiconductor substrate (front and back surfaces), separated by a dielectric layer embedded in the via. This vertical stacking approach reduces the loop area and parasitic inductance while maintaining large capacitance value, effectively resolving the contradiction between decoupling effectiveness and parasitic inductance.
2Reliability
If decoupling capacitors are placed close to load circuits to reduce parasitic inductance, then high-frequency noise filtering is improved, but the distance constraint limits placement flexibility
Solution Approach 1:
The through-semiconductor via structure enables the capacitor to be formed vertically within the substrate thickness, allowing the capacitor to be positioned immediately adjacent to the transistor electrodes without requiring lateral space. The metal plates are deposited on the front and back surfaces at locations corresponding to the transistor positions, eliminating the need for long lateral connections and providing placement flexibility throughout the substrate area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the number of different decoupling capacitor sizes needed, providing a low impedance path over a wide frequency range and improving high-frequency signal integrity by minimizing parasitic inductance, thus enhancing the decoupling performance.
Implementation Method 1
A decoupling capacitor provides a low impedance path that helps keep the voltage between the power supply and ground at its nominal voltage despite rapidly varying load demands
Implementation Method 2
A first and a second patterned metal layer are disposed on the back surface of the semiconductor substrate and are separated by a dielectric layer
Data Source
AI summary
An integrated circuit with capacitor structures includes a substrate and a plurality of vias extending from a front surface to a back surface of the substrate. A plurality of transistors is disposed at the front surface of the substrate and has first and second pluralities of electrodes. A patterned metal layer on the front surface of the semiconductor substrate provides first and second networks. The first network couples the first plurality of electrodes to a first via, and the second network couples the second plurality of electrodes to a second via. A dielectric layer separates first and second patterned metal layers on the back surface of the substrate. The first patterned metal layer includes a first metal plate coupled to the first via, and the second patterned metal layer includes a second metal plate coupled to the second via, forming a capacitor with the dielectric layer.