Back Surface Capacitor for Semiconductor Size Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing size while effectively addressing high-frequency electromagnetic noise, as external capacitor elements require significant space and internal capacitor elements necessitate large areas, complicating size reduction and noise mitigation.
Innovation Solution
A semiconductor device design featuring a capacitor element formed on the back surface of the substrate with an insulation film and overlapping wiring layer, allowing for increased capacitance without expanding the device's footprint, and reducing wiring impedance and inductance by integrating the capacitor closely with the semiconductor integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If an external capacitor element is mounted on the substrate, then large capacitance is obtained, but the device size increases
Solution Approach 1:
The capacitor element is formed by utilizing the thickness direction (z-axis) of the semiconductor substrate. The capacitor electrode extends from the front surface through the substrate to the back surface, creating a three-dimensional structure that increases capacitance without occupying additional planar area. This dimensional transition allows the capacitor to be integrated within the substrate volume rather than requiring external mounting space.
Solution Approach 2:
The capacitor element is nested within the semiconductor substrate itself. The capacitor electrode is formed inside the substrate, utilizing the substrate material as part of the capacitor structure. This nesting approach allows the capacitor to be embedded within the existing device structure, eliminating the need for separate external capacitor components and reducing overall device footprint.
2Reliability
If the semiconductor die and capacitor element are formed adjacent, then wiring impedance and inductance are reduced, but layout complexity increases
Solution Approach 1:
The capacitor element and semiconductor integrated circuit are merged into a single substrate structure. The capacitor electrode is formed within the same substrate that contains the semiconductor circuit, eliminating the need for separate capacitor components and their associated wiring. This integration reduces the wiring length connecting the capacitor to the circuit, thereby reducing impedance and inductance while simplifying the overall layout.
Solution Approach 2:
The substrate is segmented into functional regions: the front surface contains the semiconductor integrated circuit, while the back surface contains the capacitor electrode. This segmentation allows each component to be optimized for its specific function while maintaining close proximity through the substrate thickness, reducing wiring length without complicating the layout design.
3Area of stationary object
If a capacitor element is formed on the semiconductor substrate, then device size is reduced, but capacitance is insufficient for high frequency noise removal
Solution Approach 1:
The capacitance is increased by changing the geometric parameters of the capacitor electrode, specifically its area and thickness. The capacitor electrode is formed with a large area on both the front and back surfaces of the substrate, and extends through the substrate thickness. By adjusting these dimensional parameters, sufficient capacitance is achieved within the constrained substrate area, enabling effective high-frequency noise removal without increasing device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves size reduction while enhancing capacitance and effectively mitigating electromagnetic noise, even at high frequencies, by utilizing the back surface for capacitor formation, thus improving operational characteristics.
Implementation Method 1
the capacitor electrode, the insulation film and the wiring layer form a capacitor
Data Source
AI summary
The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.