Back-to-Back Die Stacking for Thinner Fan-Out Packages
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Solution Overview
Problem
Existing semiconductor packages using fan-out packaging (FOP) technology face challenges such as increased package thickness, limited thermal dissipation, and higher manufacturing complexity due to separate molding layers for each die stack level.
Innovation Solution
The implementation of a back-to-back die stacking configuration in semiconductor packages, where a first semiconductor die is stacked with a second die such that their back surfaces face each other, reduces package thickness and improves thermal and electrical performance by locating active surfaces closer to the package exterior and reducing electrical connection lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate molding layers are used for each die stack level, then each die can be properly encapsulated and protected, but package thickness increases and manufacturing complexity increases
Solution Approach 1:
The patent merges multiple separate molding layers into a single shared molding layer that encapsulates multiple die stacks simultaneously. This is achieved by forming one continuous molding layer over the carrier substrate that contains multiple recess regions, each holding a die stack, thereby reducing package thickness while maintaining proper encapsulation and protection for each die through the unified molding structure.
2Reliability
If separate molding layers are used for each die stack level, then each die can be properly encapsulated and protected, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple molding operations into a single molding process where one molding layer is formed to encapsulate multiple die stacks simultaneously. This reduces manufacturing complexity by eliminating the need for separate molding steps for each die stack level, while still providing proper encapsulation and protection through the shared molding layer with appropriately formed recess regions.
3Productivity
If active surfaces are located deeper in the package, then die stacking density increases, but thermal dissipation is limited and electrical connection lengths increase
Solution Approach 1:
The patent repositions active surfaces from deep vertical locations to shallower positions by utilizing horizontal spacing between adjacent die stacks. Multiple dies are arranged in closely spaced stacks that share a common molding layer, allowing active surfaces to be located nearer to the package exterior while maintaining high stacking density through lateral arrangement rather than deep vertical stacking.
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, semiconductor device assembly includes a first redistribution layer and a second redistribution layer, a first semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the first redistribution layer, and a second semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the second redistribution layer. The first semiconductor die may have an active surface and a back surface opposite the active surface of the first semiconductor die. The second semiconductor die may have an active surface and a back surface opposite the active surface of the second semiconductor die. The second semiconductor die may be stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die.