Back-to-Back MOS Transistors for ESD Protection
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Solution Overview
Problem
Conventional electrostatic discharge protection devices are inflexible and unable to effectively protect integrated circuits from damage caused by electrostatic discharge, especially when the operational voltage range includes negative voltages, as they often fail to provide adequate protection across the entire voltage range and can be accidentally activated during normal operations.
Innovation Solution
The design incorporates a series connection of N-type metal oxide semiconductor transistors with floating N-wells, specifically a negative voltage holding transistor and a positive voltage holding transistor, which are coupled back-to-back between an input terminal and a ground terminal, allowing for adjustable breakdown voltages to match the operational voltage range of the chip, thereby preventing accidental activation and ensuring protection from both positive and negative electrostatic discharges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common electrostatic discharge protection device is used, then it can protect the chip from currents in one direction, but it cannot protect the chip from negative voltage and has limited voltage range
Solution Approach 1:
The protection device is segmented into multiple transistor units (first transistor, second transistor, third transistor, fourth transistor) connected in series. Each transistor can handle a specific voltage range, and together they provide comprehensive protection across a wide voltage range including negative voltages. This segmentation allows the system to achieve higher adaptability while maintaining reliability.
Solution Approach 2:
Multiple transistor units are merged in a series configuration where the first and second transistors are connected in parallel between anode and cathode, and the third and fourth transistors are connected in parallel between anode and ground. This merging of multiple protection paths enables the device to handle both positive and negative voltages effectively, expanding the voltage range coverage while maintaining protection capability.
2Ease of operation
If the holding voltage is set high to avoid accidental activation, then normal operation is not disturbed, but protection against electrostatic discharge is reduced
Solution Approach 1:
The device dynamically adjusts its activation threshold based on the voltage polarity and magnitude. During normal operation within the voltage range (e.g., -3V to 3V), the transistors remain off due to their breakdown voltage characteristics. When electrostatic discharge occurs with voltage exceeding the combined breakdown voltages of the transistor series connection, the device activates to provide protection. This dynamic response allows the system to maintain ease of operation while ensuring reliability.
Solution Approach 2:
The holding voltage parameter is effectively changed by utilizing the breakdown voltage characteristics of multiple transistors in series. The combined breakdown voltage of the series-connected transistors creates a higher effective holding voltage that prevents accidental activation during normal operation, while still providing adequate protection against electrostatic discharge events. This parameter adjustment resolves the contradiction between operational stability and protection capability.
3Device complexity
If a single transistor is used for protection, then the device complexity is low, but the design is inflexible and cannot accommodate different operational voltage ranges
Solution Approach 1:
The protection device is designed with universal applicability through its multi-transistor configuration that can accommodate different operational voltage ranges. By adjusting the number and arrangement of transistor units in series and parallel, the same basic structure can be adapted to protect chips with various voltage specifications, including negative voltage operations. This universal design achieves high adaptability while maintaining reasonable structural simplicity.
Solution Approach 2:
The transistor units are nested in a structured configuration where parallel pairs (first and second transistors, third and fourth transistors) are further connected in series with each other. This nested arrangement allows for systematic scaling and adaptation to different voltage requirements while maintaining a relatively simple overall structure. The nesting principle enables design flexibility without proportionally increasing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides flexible and effective protection for integrated circuits by ensuring the electrostatic discharge protection device remains inactive within the operational voltage range, activating only when necessary to prevent damage from electrostatic discharge currents, thus safeguarding the chip from both positive and negative voltage-induced damage.
Implementation Method 1
Electrostatic discharge is an effect due to electrical charges in an object flowing to another object through a discharging path when two electrically charged objects contact or short to each other. The electrostatic discharge can generate huge currents in a very short time
Implementation Method 2
the holding voltage of the electrostatic discharge protection device should be greater than 1.5V so that the electrostatic discharge protection device will not be turned on when an input voltage of the chip is 1.5V
Data Source
AI summary
An electrostatic discharge protection device includes an anode, a cathode, a negative voltage holding transistor and a positive voltage holding transistor. The anode is coupled to an input terminal, and the cathode is coupled to a ground. The negative voltage holding transistor includes an N-well. The positive voltage holding transistor includes an N-well. The N-well of the positive voltage holding transistor and the N-well of the negative voltage holding transistor are coupled together and are float. The negative voltage holding transistor and the positive voltage holding transistor are coupled between the anode and the cathode in a manner of back-to-back.