Back-to-Back Via Spacer Layout for Dense Logic Cells
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating small-scale back-to-back vias for logic cells due to the difficulty in reliably patterning and isolating vias at close distances, leading to potential shorts and the need for expensive fabrication processes like EUV lithography.
Innovation Solution
The use of a spacer, typically made of silicon nitride, to separate small-pitch back-to-back vias in adjacent logic cells, allowing for their fabrication using conventional and cost-effective techniques such as trench-based patterning and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional patterning techniques are used to fabricate small-pitch back-to-back vias, then manufacturing cost is reduced, but manufacturing precision deteriorates leading to potential shorts
Solution Approach 1:
A spacer structure is introduced as an intermediary element between adjacent vias. The spacer is formed by depositing a dielectric material conformally over a mandrel structure, then selectively removing portions to create isolation regions. This intermediary structure enables precise via separation using conventional patterning techniques while preventing shorts that would otherwise occur with small-pitch via fabrication.
2Area of stationary object
If logic cell track size is reduced from 6T to 5T or fewer tracks, then area density is improved, but manufacturing precision deteriorates due to difficulty in patterning and isolating vias at close distances
Solution Approach 1:
The logic cell structure is segmented into distinct regions separated by spacer structures. The spacer divides the cell into regions containing individual vias, allowing each via to be patterned and isolated independently. This segmentation enables the fabrication of compact logic cells with reduced track sizes while maintaining via patterning precision through the use of spacer-defined isolation regions.
3Area of stationary object
If back-to-back vias are placed at very small pitches to increase density, then area density is improved, but reliability deteriorates due to increased risk of shorts between adjacent vias
Solution Approach 1:
The spacer structure serves as a reliable intermediary barrier between back-to-back vias placed at very small pitches. The spacer is formed using conformal deposition techniques that ensure uniform thickness and complete coverage, creating a dependable isolation layer that prevents electrical shorts while allowing the vias to be positioned at minimal spacing for maximum density.
Solution Approach 2:
The spacer structure enables parameter changes in the via configuration by providing a fixed reference dimension for via placement. By controlling the spacer thickness and mandrel dimensions, the design can accommodate very small via pitches while maintaining adequate isolation, thus changing the geometric parameters to achieve both high density and high reliability.
Data Source
AI summary
An electronic device having at least two adjacent logic cells is disclosed. The electronic device includes at least one pair of back-to-back vias, wherein a first via of the pair of back-to-back vias is associated with a first logic cell of the at least two adjacent logic cells and a second via of the pair of back-to-back vias is associated with a second logic cell of the at least two adjacent logic cells; and a spacer disposed between and separating the first via and the second via.