Back-Well IC Structure Using Resistive Semiconductor Isolation
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Solution Overview
Problem
In atomic-level scaled micro-devices, the size and scale of biasing terminals can reduce electrical properties such as threshold voltage and trigger current to undesirable levels, posing a risk to the functionality of circuit chips.
Innovation Solution
An integrated circuit structure incorporating a semiconductor substrate with a deep well, a device within the well, and a resistive semiconductor material interposed between the device and a back well, which electrically couples the doped semiconductor materials to control biasing effects and maintain desired electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the biasing terminal is scaled down to atomic level, then the device size is reduced, but the electrical properties (threshold voltage, trigger current) are reduced to undesirable levels
Solution Approach 1:
The patent divides the semiconductor structure into distinct segments: a deep well region, a back well region, and a resistive semiconductor material region. This segmentation allows the biasing terminal to be scaled down while the resistive material segment maintains proper electrical properties by providing controlled resistance between the deep well and back well, preventing unwanted coupling effects that would otherwise degrade threshold voltage and trigger current.
Solution Approach 2:
The resistive semiconductor material acts as an intermediary element between the deep well and back well. This intermediary provides controlled electrical resistance that isolates the scaled-down biasing terminal from unwanted electrical interactions, thereby maintaining desirable threshold voltage and trigger current levels even when the overall device size is reduced to atomic level scaling.
2Productivity
If the biasing terminal size is reduced, then integration density increases, but the trigger current and threshold voltage fall below desired values
Solution Approach 1:
The patent applies local quality by creating a region with specifically engineered resistive semiconductor material properties in the deep well. This localized resistive region provides the necessary electrical characteristics (controlled resistance) precisely where needed, allowing the biasing terminal to be minimized for high integration density while maintaining proper trigger current and threshold voltage through the localized resistive effect.
Solution Approach 2:
The patent changes the electrical parameters of the semiconductor material by creating a resistive region with specific resistance characteristics. By controlling the resistance parameter in the deep well region, the patent enables the biasing terminal to operate at reduced size for higher integration density while maintaining desirable trigger current and threshold voltage levels through the modified electrical parameter landscape.
3Reliability
If deep well and back well are directly coupled, then electrical connectivity is improved, but biasing effects are enhanced excessively
Solution Approach 1:
The resistive semiconductor material serves as an intermediary between the deep well and back well, allowing controlled electrical connectivity while preventing excessive biasing effects. The intermediary's resistance property enables necessary electrical connection for device operation while attenuating unwanted biasing interactions between the two well regions.
Solution Approach 2:
The patent converts the potentially harmful excessive biasing effects into a beneficial controlled resistance characteristic. By introducing the resistive semiconductor material, the unwanted strong coupling between deep well and back well is transformed into a useful controlled resistance that maintains electrical connectivity while preventing harmful biasing interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resistive semiconductor material within the deep well reduces the impact of biasing on the device, maintaining or enhancing threshold voltage and trigger current levels, thereby improving the operational reliability of micro-devices like transistors and ESD devices.
Implementation Method 1
a first resistive semiconductor material within the deep well and interposed between the first portion of the deep well and the second portion of the deep well
Data Source
AI summary
Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.