Backchannel Modulation for High-Speed Network Initialization
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Solution Overview
Problem
High-speed wired network communications face challenges during link initialization, where backchannel communication and equalizer setting adjustments are hindered by prevalent bit errors at high link rates, necessitating mode shifting and synchronization, which increases complexity and risk as link speeds increase.
Innovation Solution
The system modulates low-rate backchannel information onto a high-rate bit stream, allowing continuous and simultaneous backchannel and equalizer setting communications, avoiding mode shifting and enabling reliable communication even during equalizer adjustments by encoding and modulating low-rate bits onto high-rate sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If backchannel communication is performed at high link rate during equalizer adjustment, then communication speed is improved, but bit errors increase making reliable communication difficult
Solution Approach 1:
The system performs preliminary equalizer adjustments at a lower training rate before transitioning to high-speed data mode. This preliminary action ensures that the equalizer is properly calibrated to handle link characteristics, thereby reducing bit errors when high-rate backchannel communication subsequently occurs.
Solution Approach 2:
The system employs periodic training sequences inserted at regular intervals during high-speed operation. These training sequences allow the equalizer to continuously adapt and correct for link impairments, maintaining communication reliability even at high data rates.
2Reliability
If mode shifting between backchannel mode and equalizer adjustment mode is implemented, then communication reliability is improved, but initialization time increases
Solution Approach 1:
The system merges backchannel communication with equalizer adjustment operations by allowing both to occur simultaneously at the same operating rate. This eliminates the need for separate mode shifting between backchannel mode and equalizer adjustment mode, thereby reducing initialization time while maintaining reliability through continuous equalizer training.
3Reliability
If mode shifting is performed, then communication reliability is improved, but system complexity increases due to synchronization requirements
Solution Approach 1:
The system combines backchannel communication and equalizer adjustment into a single unified mode operating at the same data rate. This merging eliminates the need for complex synchronization mechanisms required when switching between different modes, thereby reducing system complexity while maintaining communication reliability.
4Reliability
If equalizer retraining is performed after mode shift, then communication reliability is improved, but initialization time increases
Solution Approach 1:
The system maintains continuous equalizer training throughout operation by periodically inserting training sequences during high-speed data mode. This continuous training approach eliminates the need for separate retraining periods after mode shifts, thereby reducing initialization time while maintaining equalizer performance and communication reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables robust backchannel communication and equalizer adjustments at high link rates, reducing initialization time and minimizing errors, while accommodating polarity inversions and clock mismatches, thus improving the reliability and efficiency of link initialization.
Implementation Method 1
a modulation module configured to generate the high rate bit stream and to modulate the low rate bit stream with the encoded low rate bit stream
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
One embodiment provides a network controller. The network controller includes physical interface (PHY) circuitry comprising transmitter circuitry configured to transmit data frames to a link partner in communication with the transmit circuitry over a channel link. The network controller also includes a link speed cycling module configured to, upon initialization of the PHY circuitry, cause the transmitter circuitry to transmit data frames to the link partner using at least one high rate link speed. The network controller also includes an equalization presets module configured to apply at least one equalization preset setting to the transmitter circuitry while the transmitter circuitry is transmitting the data frames to the link partner. The link speed module is further configured to cause the transmitter circuitry to dwell, for a transmitter dwell time period, for the at least one equalization preset setting at the at least one high rate link speed. The transmitter dwell time period is sufficient to allow the link partner to lock on to the transmitted data frames.