Backdrilled PCB Via Layout for Signal Integrity and Power Planes
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Solution Overview
Problem
Backdrilling processes in multi-layer printed circuit boards (PCBs) to eliminate via stubs cause unwanted signal reflections and undermine the effectiveness of ground and power planes due to the application of uniform backdrill clearance regions, leading to reduced signal integrity and current-carrying capacity.
Innovation Solution
Selective elimination of backdrill clearance regions on voltage planes with the same reference voltage, while maintaining clearance on other layers, to increase the copper web width and improve signal-to-ground reference and current delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform backdrill clearance regions are applied to all layers, then signal reflections are reduced, but the copper web width and current-carrying capacity of voltage planes are reduced
Solution Approach 1:
The patent applies different clearance region designs to different layers based on their specific functions. Signal layers maintain backdrill clearance regions to prevent signal reflections and ensure signal integrity. Voltage planes selectively eliminate backdrill clearance regions where they can abut backdrilled shafts to maintain copper web width and current-carrying capacity, while still maintaining clearance regions where needed to prevent electrical shorting. This local differentiation resolves the contradiction by optimizing each layer's clearance region design according to its specific electrical requirements.
2Quantity of substance
If backdrill clearance regions are eliminated on voltage planes, then current-carrying capacity is improved, but the risk of electrical shorting between conductive elements increases
Solution Approach 1:
The patent selectively eliminates backdrill clearance regions only on voltage plane layers where the eliminated regions will abut backdrilled shafts, rather than universally eliminating them across all layers. This localized approach maintains copper web width and current-carrying capacity where beneficial, while preserving clearance regions on signal layers and on voltage planes where they are needed to prevent electrical shorting. The selective application resolves the contradiction by applying clearance region elimination only where it provides benefit without creating harmful effects.
Solution Approach 2:
The patent segments the PCB into different functional layers (signal layers and voltage plane layers) and applies different backdrill clearance region designs to each segment. Signal layers maintain uniform backdrill clearance regions to prevent signal reflections, while voltage plane layers selectively eliminate clearance regions to maintain copper web width. This segmentation allows the patent to optimize signal integrity and current-carrying capacity independently, resolving the contradiction between these two competing requirements.
3Object-affected harmful factors
If backdrill clearance regions are maintained on all layers, then electrical shorting is prevented, but signal-to-ground reference and copper web effectiveness are reduced
Solution Approach 1:
The patent applies different clearance region designs to different layers based on their specific electrical requirements. Signal layers maintain backdrill clearance regions to ensure proper signal-to-ground reference and prevent signal reflections. Voltage planes selectively eliminate backdrill clearance regions where they can abut backdrilled shafts to maintain copper web width and effectiveness, while preserving clearance regions where needed to prevent electrical shorting. This local differentiation resolves the contradiction by optimizing clearance region design for each layer's specific function.
Data Source
AI summary
A multi-layer printed circuit board (PCB), includes a first plurality of layers, each having a plurality of signal traces disposed thereon, a second plurality of layers, each having a voltage plane disposed thereon, and a plurality of plated-through-hole vias disposed between a first surface of the multi-layer PCB and a second surface of the multi-layer PCB, wherein each plated-through-hole via includes a conductive barrel, wherein a first layer of the first plurality of layers includes a backdrill clearance region around a first plated-through-hole via in which no signal traces are disposed, and a first voltage plane on a first layer of the second plurality of layers is in contact with the conductive barrel of the first plated-through-hole via. In various embodiments, portions of the barrel of a plated-through-hole via are removed by, for example, backdrilling. Various embodiments advantageously provide improvements to signal-to-reference overlap, and to power plane current-carrying capacity.