Backend Refresh Reads for Lower First-Read Bit Errors in Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory sub-systems face issues with high first read raw bit error rate (RBER) and trigger rate due to data degradation mechanisms like data retention and read disturb, leading to reliability and performance problems, especially in large capacity drives, without effective feedback mechanisms to ensure data integrity during writeback operations.

Innovation Solution

Performing periodic read operations on every block of the memory die, identifying the page with the lowest sensing overhead, and refreshing the block without data transfer, maintaining blocks in a T-state with low RBER and trigger rate, thereby reducing first read issues and improving runtime performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If periodic read operations are performed on every block to reduce first read RBER, then data integrity is improved, but backend traffic and sensing overhead increase

Engineering Contradiction:
Improvefirst read raw bit error rateVSAvoidsensing overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by performing read operations selectively on specific pages within blocks rather than uniformly on all pages. The system identifies and reads only the pages that are most susceptible to data degradation (those with highest RBER), thereby reducing overall sensing overhead while maintaining data integrity for the most vulnerable data portions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically adjusts read parameters including voltage levels, timing sequences, and page selection criteria based on detected RBER patterns and data age. By changing these parameters adaptively, the system optimizes the balance between error correction effectiveness and backend traffic generation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If frequent read operations are performed to maintain blocks in T-state, then data retention is improved, but read disturb effects increase

Engineering Contradiction:
Improvedata retentionVSAvoidlatent read disturb
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent implements periodic read operations at optimized intervals rather than continuous or frequent reads. The system determines optimal read periods based on data age, block usage patterns, and temperature conditions, performing reads only when necessary to maintain data integrity while minimizing cumulative read disturb effects on the memory cells.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system skips read operations on pages that have recently been accessed or are less susceptible to data degradation. By identifying and skipping already-refreshed pages, the system reduces unnecessary read disturb while still maintaining T-state for vulnerable pages through targeted read operations.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If backend refresh reads are performed to reduce trigger rate, then data integrity is improved, but runtime performance decreases

Engineering Contradiction:
Improvetrigger rateVSAvoidruntime performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary identification of pages requiring refresh based on metadata, access patterns, and data age before executing actual read operations. This preliminary sorting and prioritization allows the system to focus refresh efforts on the most critical pages, reducing overall backend traffic and improving runtime performance while maintaining data integrity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies partial action by performing refresh operations on only a subset of pages within each block - specifically those pages identified as having highest risk of data degradation. This selective approach reduces the total number of read operations compared to refreshing all pages, thereby improving runtime performance while still achieving the goal of reducing trigger rate.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12488828B2Efficient periodic backend refresh reads for reducing bit error rate in memory devices
Publication Date: 2025.12.02 MICRON TECHNOLOGY INC
  • US12488828B2 patent drawing
  • US12488828B2 patent drawing
  • US12488828B2 patent drawing

AI summary

A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.