Backend TFT Ferroelectric Memory Cells for Dense Embedded Arrays
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Solution Overview
Problem
The scaling of ferroelectric capacitors in integrated circuits is challenging due to area reductions in dielectric structures and polarization charge storage, making it difficult to integrate them in advanced semiconductor technologies like 10 nm, 7 nm, and 5 nm nodes.
Innovation Solution
The integration of a ferroelectric capacitor electrically coupled with a backend thin-film transistor (TFT) in an embedded one-transistor one-capacitor (1T1C) memory cell, allowing the memory array to be embedded in upper metal layers, which increases memory density and scalability by using the backend TFT to tuck sensing peripherals underneath the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ferroelectric capacitors are scaled to smaller process technologies (10 nm, 7 nm, 5 nm nodes), then device integration density is improved, but dielectric structure area and polarization charge storage are reduced
Solution Approach 1:
The patent moves the transistor from the front-end to the back-end of the fabrication process, allowing the capacitor dielectric structure to extend into upper metal layers (third, fourth, and higher interconnect layers). This vertical dimensionality change enables the capacitor to occupy three-dimensional space rather than being constrained to a single planar layer, thereby maintaining sufficient dielectric area even as process nodes scale down.
Solution Approach 2:
The patent separates the capacitor structure into multiple segments across different metal layers. The dielectric material is distributed across the third, fourth, and higher interconnect layers, with each layer contributing to the total capacitance. This segmentation allows the total dielectric area to be maintained by summing contributions from multiple smaller areas across different layers.
2Productivity
If ferroelectric capacitors are scaled to smaller process technologies, then integration density is improved, but polarization charge storage is reduced
Solution Approach 1:
By extending the capacitor dielectric structure vertically across multiple metal layers (third, fourth, and higher interconnect layers), the patent increases the total volume available for polarization charge storage. This vertical expansion compensates for the reduced charge storage capacity that would result from planar scaling to smaller process nodes.
Solution Approach 2:
The patent employs a composite capacitor structure where the dielectric material is distributed across multiple metal layers, each contributing to the total capacitance. This composite arrangement allows the sum of polarization charges from multiple smaller dielectric segments to equal or exceed the charge storage of a single large dielectric structure, thereby maintaining adequate charge storage while achieving higher integration density.
3Productivity
If memory array is embedded in upper metal layers with backend TFT, then memory density is improved, but device complexity is increased
Solution Approach 1:
The patent inverts the conventional fabrication sequence by placing the transistor at the back-end rather than the front-end. This inversion allows the capacitor dielectric to be formed first in the upper metal layers, simplifying the capacitor fabrication process. The transistor is then integrated afterward, connecting to the pre-formed capacitor structure, which reduces the overall process complexity despite the unusual architecture.
Solution Approach 2:
The upper metal layers serve multiple functions: they act as interconnect layers for signal routing and simultaneously host the capacitor dielectric structures for data storage. This multi-functionality eliminates the need for separate dedicated capacitor layers, reducing the total number of fabrication steps and simplifying the overall device architecture while maintaining high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher memory density and performance while allowing ferroelectric capacitors to function effectively even in smaller process technologies, providing a feasible path for integration across different process nodes with relaxed design rules.
Implementation Method 1
a ferroelectric capacitor electrically coupled to a backend transistor... a ferroelectric dielectric between the first and second terminals
Data Source
AI summary
An integrated circuit includes a backend thin-film transistor (TFT) a ferroelectric capacitor electrically connected to the backend TFT. The backend TFT has a gate electrode, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, and a gate dielectric between the gate electrode and semiconductor region. The ferroelectric capacitor has a first terminal electrically connected to one of the source and drain regions, a second terminal, and a ferroelectric dielectric between the first and second terminals. In an embodiment, a memory cell includes this integrated circuit, the gate electrode being electrically connected to a wordline, the source region being electrically coupled to a bitline, and the drain region being the one of the source and drain regions. In an embodiment, an embedded memory includes wordlines, bitlines, and a plurality of such memory cells at crossing regions of the wordlines and bitlines.