Backend Transistor Formation Using Seeded Epitaxial Growth
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Solution Overview
Problem
The scaling of features in integrated circuits (ICs) has led to challenges in optimizing fabrication and performance of backend transistors, particularly due to the high cost and susceptibility to defects associated with layer transfer techniques.
Innovation Solution
The use of seeded epitaxial growth techniques to form backend transistors, where a seed structure in an interconnect layer is used to deposit a semiconductor material with a matching crystal orientation, allowing for the formation of a channel region without the need for layer transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If layer transfer techniques are used to form backend transistors, then transistor formation is enabled in scaled IC structures, but cost increases and defect susceptibility increases
Solution Approach 1:
The patent extracts and eliminates the layer transfer step from the fabrication process. Instead of transferring semiconductor layers from a separate wafer, the method forms backend transistors directly in the original IC structure using selective epitaxial growth in recessed regions, thereby removing the source of defects associated with layer transfer while maintaining transistor formation capability
Solution Approach 2:
The patent performs preliminary actions by forming recessed regions in the semiconductor layer before final transistor formation. These recesses are prepared in advance with specific geometries and positions, allowing subsequent epitaxial growth to occur only in desired locations, thus enabling backend transistor formation without requiring defect-prone layer transfer operations
2Ease of manufacture
If layer transfer techniques are used to form backend transistors, then transistor formation is enabled in scaled IC structures, but defect susceptibility increases
Solution Approach 1:
The patent removes the layer transfer operation entirely from the fabrication sequence. Backend transistors are formed in-situ using selective epitaxial growth in recessed regions of the semiconductor layer, eliminating the interface defects and contamination that inherently arise from transferring layers between wafers
Solution Approach 2:
The patent introduces recessed regions as intermediary structures that mediate between the planar semiconductor layer and the three-dimensional transistor structures. These recesses serve as confined growth zones that guide epitaxial material deposition, enabling precise backend transistor formation without the need for external layer transfer operations
3Productivity
If transistor size is reduced to increase device density, then capacity increases, but fabrication optimization becomes more difficult
Solution Approach 1:
The patent applies local quality by creating spatially varying structures within the semiconductor layer. Recessed regions are formed at specific locations to accommodate backend transistors, while other regions maintain their original planar configuration for frontend devices. This local differentiation enables scaled transistor dimensions in specific areas without compromising overall fabrication processability
Solution Approach 2:
The patent segments the semiconductor layer into distinct functional regions: recessed areas for backend transistor formation and non-recessed areas for frontend devices. This segmentation allows independent optimization of each region's transistor characteristics and fabrication parameters, facilitating density increases through scaled features while maintaining ease of manufacture through region-specific process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality backend transistors at lower cost and with reduced defects, facilitating the development of monolithic three-dimensional IC structures with improved performance and reliability.
Implementation Method 1
a seed structure in an interconnect layer is used to deposit a layer of a semiconductor material having a substantially same crystal orientation as the seed structure
Data Source
AI summary
Disclosed herein are integrated circuit (IC) structures with backend transistors, including backend transistors fabricated using seeded epitaxial growth techniques. In one example, an IC structure includes a semiconductor structure (e.g., a seed structure) over an interconnect layer, where the semiconductor structure includes a first semiconductor material with a first crystal lattice orientation, and a second semiconductor material over the semiconductor structure, where the second semiconductor material has a second crystal lattice orientation that is substantially the same as the first crystal lattice orientation, and where a portion of the second semiconductor material is a channel region of a backend transistor. In one example, the IC structure may also include a third semiconductor material (e.g., a textured template material) between the seed structure and the second semiconductor material.