Background Memory Scrubbing for Idle-Cycle Error Detection
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Solution Overview
Problem
Existing memory testing technologies in mission-critical systems, such as automotive and industrial automation, face challenges in detecting errors in memory blocks that are infrequently accessed, as single-bit parity schemes fail to detect double-bit errors, and error correction codes require frequent access to detect bit errors effectively, which can lead to undetected errors in less accessed memory locations.
Innovation Solution
The implementation of a background memory test apparatus (BGMTA) that includes a schedulable memory scrubbing circuit for parity/ECC memory arrays and a known-state memory test circuit, which operate in parallel with processor execution, sequentially reading memory blocks during system bus idle cycles to perform periodic or continuous integrity testing, using CRC calculations for known-state memories and error detection for parity/ECC memories, thereby increasing the likelihood of error detection with minimal processor overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-bit parity schemes are used for memory error detection, then device complexity is reduced, but measurement precision deteriorates because double-bit errors cannot be detected
Solution Approach 1:
The memory array is segmented into multiple blocks, each with its own parity bits. This allows independent error detection in each block while maintaining overall system simplicity. The segmentation enables the system to use simple parity checks locally while achieving more comprehensive error detection coverage system-wide.
Solution Approach 2:
The patent implements periodic background testing of memory blocks using the parity check circuits. Instead of continuous monitoring that would increase complexity, the system performs periodic checks during normal operation, maintaining simple hardware while achieving thorough error detection over time through repeated sampling of memory blocks.
2Measurement precision
If error correction codes (ECC) are used for memory testing, then measurement precision is improved for detecting bit errors, but productivity deteriorates due to frequent access requirements
Solution Approach 1:
The system performs periodic background testing of memory blocks using parity checks during normal processor operation. This periodic sampling achieves thorough error detection without requiring continuous memory access, thus maintaining high system throughput while still providing accurate error detection capability.
Solution Approach 2:
The memory system performs self-testing through background parity check operations that automatically monitor memory blocks during normal operation. This self-service mechanism detects errors without external intervention or frequent processor involvement, maintaining productivity while ensuring measurement precision through continuous background monitoring.
3Measurement precision
If frequent memory access is performed for error detection, then measurement precision is improved, but productivity deteriorates due to impact on system throughput
Solution Approach 1:
The patent implements periodic background testing that samples memory blocks at intervals during normal operation. This periodic approach achieves adequate error detection precision through repeated monitoring without requiring continuous memory access, thus maintaining high system throughput while still providing thorough error detection coverage over time.
Solution Approach 2:
The background parity check circuitry operates continuously in the background during normal processor operation, providing ongoing error detection capability. This continuous background monitoring maintains measurement precision through persistent surveillance without interrupting or slowing down the main processor operations, thereby preserving productivity.
4Reliability
If background testing is performed during processor execution, then reliability is improved, but device complexity increases due to additional test circuits
Solution Approach 1:
The background test circuits utilize the existing memory bus and controller resources for both normal processor operations and background testing. The parity check circuits serve dual purposes: they support normal memory operations while simultaneously performing error detection during background testing modes, thereby improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The memory system incorporates self-testing capability through background parity check operations that automatically monitor memory blocks during normal operation. This self-service mechanism provides improved reliability through continuous error detection without requiring complex external test equipment or sophisticated test control circuits, as the system tests itself using its own existing resources.
Data Source
AI summary
A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.