Backless Cache Lines for Lazy Physical Memory Allocation
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Solution Overview
Problem
In computer processing systems, the existing memory hierarchy faces inefficiencies due to the need for power-hungry and large hardware to perform alias disambiguation, page mapping, and access control before cache access, which hinders performance and increases power consumption.
Innovation Solution
A computer processing system with a hierarchical memory system that includes virtual and physical caches, utilizing backless cache lines that can be referenced by virtual addresses without corresponding physical addresses, allowing for lazy allocation and initialization of physical memory, and employing a protection lookaside buffer to manage illegal addresses, thereby reducing the need for pre-allocated physical memory and minimizing operating system involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alias disambiguation, page mapping, and access control are performed before cache access using traditional hardware, then address management is achieved, but power consumption increases and hardware size grows
Solution Approach 1:
The patent extracts the alias disambiguation, page mapping, and access control functions from the traditional pre-cache hardware path and relocates them to operate on cache lines after they are already in the cache. This removes the power-hungry hardware from the critical path while maintaining address management functionality through software-based mechanisms.
Solution Approach 2:
The patent introduces a page table entry with a pending bit as an intermediary mechanism to track the backing status of cache lines. This intermediary structure enables the system to manage address mapping and access control without requiring dedicated hardware in the pre-cache path, thereby reducing power consumption while maintaining reliability.
2Reliability
If physical memory is pre-allocated for all virtual addresses, then address mapping is ensured, but memory capacity is wasted and hardware requirements increase
Solution Approach 1:
The patent applies preliminary action by setting up the virtual address space and page table structures in advance, but defers the actual physical memory allocation until it is truly needed. The pending bit in page table entries marks which virtual addresses require physical backing, allowing the system to prepare address mapping structures without immediately consuming physical memory capacity.
Solution Approach 2:
The patent treats physical memory allocation as a disposable resource that is allocated only when needed and can be freed when no longer required. By using backless cache lines that don't require immediate physical backing, the system can allocate and deallocate physical memory dynamically, avoiding permanent reservation of memory capacity for all possible virtual addresses.
3Productivity
If cache lines are evicted frequently to maintain cache hit rate, then cache performance improves, but memory traffic increases
Solution Approach 1:
The patent changes the parameter of cache line backing status from binary (backed/not backed) to a spectrum that includes pending states. By allowing cache lines to remain in cache with pending page table entries, the system can retain useful data in cache without immediately evicting it to maintain hit rates, thereby reducing memory traffic while preserving productivity.
Data Source
AI summary
A computer processing system with a hierarchical memory system having at least one cache and physical memory, and a processor having execution logic that generates memory requests that are supplied to the hierarchical memory system. The at least one cache stores a plurality of cache lines including at least one backless cache line.