Backmetal Semiconductor Structure for Thin Die Low ON Resistance
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Solution Overview
Problem
Semiconductor fabrication processes face challenges in efficiently forming thin semiconductor devices with optimal electrical and thermal properties, particularly in achieving low ON resistance and compact package size, due to limitations in wafer thickness and backmetal layer thickness ratios.
Innovation Solution
The implementation of semiconductor devices with a die thickness less than 30 micrometers and a metal layer thickness ratio of no more than four times the die thickness, coupled with a mold compound and backgrinding techniques to form recesses and pattern metal layers, allowing for efficient singulation and reduced ON resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the die thickness is reduced to less than 30 micrometers, then the package size is reduced, but the manufacturing precision and structural integrity become more difficult to maintain
Solution Approach 1:
The patent applies parameter changes by precisely controlling the die thickness to be less than 30 micrometers and the backmetal layer thickness to be between 5-20 micrometers, optimizing the thickness ratio to achieve low ON resistance while maintaining structural integrity through controlled parameter relationships
Solution Approach 2:
The patent uses composite materials by combining the silicon die with a backmetal layer (copper, aluminum, or tungsten) and mold compound, creating a composite structure that provides both mechanical support and electrical functionality while enabling thin-profile packaging
2Reliability
If the backmetal layer thickness is increased to reduce ON resistance, then the electrical conductivity is improved, but the overall device thickness and package size increase
Solution Approach 1:
The patent optimizes the backmetal layer thickness parameter to be between 5-20 micrometers, which is sufficient to achieve low ON resistance (below 1.0 milliohm) while maintaining the overall device thickness within acceptable limits for compact packaging
Solution Approach 2:
The patent applies partial action by providing just enough backmetal layer thickness (5-20 micrometers) to achieve the required electrical performance without excessive material, balancing conductivity needs with package size constraints
3Volume of moving object
If the die thickness is reduced for compact packaging, then the package size is decreased, but the thermal management and electrical performance become more challenging
Solution Approach 1:
The patent uses composite materials including copper or aluminum backmetal layers with high thermal conductivity combined with the silicon die, creating a thermally efficient structure that manages heat effectively despite the reduced die thickness
Solution Approach 2:
The backmetal layer serves as an intermediary that provides both electrical connectivity and thermal management functions, facilitating heat dissipation from the die while maintaining the thin-profile structure required for compact packaging
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with decreased ON resistance and reduced package size, suitable for applications like rapid charging systems, by optimizing the thickness ratio of the silicon die to the backmetal layer and incorporating a mold compound for protection and oxidation prevention.
Implementation Method 1
incorporating a mold compound for protection and oxidation prevention
Data Source
AI summary
Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.