Backplane Clock Synchronization via External Phase Comparison
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Solution Overview
Problem
In instrumentation systems, synchronizing clocks across multiple chassis connected via networks is challenging due to the lack of efficient methods for disciplining slave clocks to master clocks, leading to potential phase and frequency misalignments.
Innovation Solution
An apparatus with a backplane, a clock, and a processing element configured to compare time information from the clock with external time information via a synchronization interface, determining adjustment information to synchronize the clock with an external clock using protocols like IEEE 1588 or GPS, ensuring phase and frequency alignment across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple instrumentation chassis are connected via network, then system versatility and measurement capability are improved, but clock synchronization precision deteriorates due to phase and frequency misalignments
Solution Approach 1:
The patent implements a feedback mechanism where the processing element continuously monitors the phase and frequency of the backplane clock against the external clock received via network, and dynamically adjusts the backplane clock parameters to maintain synchronization, resolving the clock alignment issue in multi-chassis systems
Solution Approach 2:
The patent changes the parameters of the backplane clock (phase and frequency) based on comparison with external clock signals received through the synchronization interface, enabling precise clock synchronization across network-connected chassis while maintaining system versatility
2Reliability
If slave clock is disciplined to master clock via network protocol, then clock synchronization is improved, but system complexity increases due to additional synchronization interface and processing requirements
Solution Approach 1:
The processing element is designed to perform multiple functions: it processes backplane operations, receives external clock signals via the synchronization interface, compares clock phases and frequencies, and controls clock adjustments. This multi-functionality reduces the need for separate dedicated synchronization hardware, managing complexity while improving reliability
3Measurement precision
If backplane clock is synchronized with external clock, then timing accuracy across modules is improved, but processing time increases due to clock comparison and adjustment operations
Solution Approach 1:
The system performs preliminary clock synchronization by comparing the backplane clock with the external clock and making adjustments in advance, ensuring that timing accuracy is maintained before critical measurement operations begin, thereby minimizing the impact of synchronization processing on overall measurement time
Data Source
AI summary
Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.