Backplane-Free Shelf Interconnect for Server Heat Dissipation
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Solution Overview
Problem
Conventional electronic devices with multiple CPUs and xPUs connected through a backplane face issues with heat dissipation and signal integrity, necessitating the use of a retimer chip to resolve high-speed link problems, which affects flexibility, convenience, and cost-effectiveness of shelf stacking and expansion.
Innovation Solution
A backplane-free design is implemented, allowing connectors in each shelf to be connected via cables, with evenly distributed processors and optional target proportions, and incorporating a heat dissipation system with heat sinks and liquid-assisted air cooling to enhance heat dissipation without requiring a retimer chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CPUs and xPUs are connected through a backplane in the same shelf, then signal transmission is achieved, but heat dissipation capability deteriorates and signal integrity loss increases
Solution Approach 1:
The system divides the computing components into separate shelves, with each shelf containing its own CPU and xPU components. This segmentation allows independent heat dissipation management for each shelf while maintaining signal integrity through direct connectors, resolving the contradiction between heat dissipation and signal transmission.
Solution Approach 2:
The patent transitions from a two-dimensional backplane connection within a single shelf to a three-dimensional multi-shelf architecture where connectors in different shelves are directly connected. This dimensional change enables better heat dissipation space while maintaining signal integrity through direct physical connections.
2Reliability
If a retimer chip is added to resolve high-speed link problems, then signal integrity is improved, but device complexity and cost increase
Solution Approach 1:
The patent removes the need for retimer chips by extracting the signal integrity solution from the component level and implementing it at the architectural level through direct connector connections between shelves. This eliminates the harmful factor of additional chips while maintaining high-speed link performance.
3Ease of operation
If all CPUs and xPUs are located in the same shelf, then connection through backplane is achieved, but heat dissipation and maintenance flexibility deteriorate
Solution Approach 1:
By segmenting components into separate shelves, the system enables independent maintenance of each shelf without affecting other components. Each shelf can be accessed, removed, or replaced independently, improving maintenance flexibility while distributing heat generation across multiple locations.
4Adaptability or versatility
If backplane design is used for connecting components, then signal transmission is achieved, but heat dissipation capability and adaptability deteriorate
Solution Approach 1:
The patent implements a dynamic architecture where shelves can be independently added, removed, or reconfigured through direct connector connections. This dynamic design provides adaptability for different deployment scenarios while each shelf maintains its own heat dissipation independence, unlike the fixed backplane structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves heat dissipation capability, enhances flexibility and cost-effectiveness, and simplifies maintenance by eliminating the need for a retimer chip, while allowing for flexible shelf stacking and expansion.
Implementation Method 1
incorporating a heat dissipation system with heat sinks and liquid-assisted air cooling to enhance heat dissipation
Data Source
Figure 1
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Figure 2B
AI summary
This application provides an electronic device and a heat dissipation system. The electronic device includes a plurality of shelves. Each shelf includes a first processor, a first mainboard, and a connector. The first mainboard in any shelf is separately connected to the first processor and the connector that are located in the same shelf. The connector in a first shelf is separately connected to the connector in at least one second shelf. Therefore, in this application, a heat dissipation capability of the electronic device is improved through backplane-free design of the electronic device, and an additional chip does not need to be used to resolve a high-speed link problem. In addition, flexibility, convenience, and cost-effectiveness of shelf stacking and expansion of the electronic device can be further improved.