Backplane Shift Register Design for Reliable AMOLED Gate Driving
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Solution Overview
Problem
The existing Gate Driver On Array (GOA) designs in AMOLED displays face reliability issues due to the use of thin film transistors and capacitors, necessitating a cost-effective and reliable alternative to gate driving integrated circuits (Gate IC) for narrow bezel designs.
Innovation Solution
A shift register unit is fabricated using backplane array process, incorporating input, control, and output circuits with transistors and capacitors to provide various waveforms and enhance reliability, utilizing a cascade configuration with staggered clock signals to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Gate Driver On Array (GOA) is used instead of Gate IC to reduce design cost and achieve narrow bezel design, then cost and bezel size are improved, but reliability deteriorates due to the use of thin film transistors and capacitors
Solution Approach 1:
The shift register unit is divided into multiple functional modules: first input circuit (transistors T3-T4), second input circuit (transistors T1-T2), control circuit (transistor T7), and output circuit (transistors T5-T6). Each module performs a specific function in the signal processing chain, allowing the complex shift register to be constructed from manageable, reliable sub-circuits that can be independently optimized and tested.
2Reliability
If more thin film transistors and capacitors are used to improve GOA reliability, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The shift register unit employs a standardized set of circuit blocks that can be repeatedly instantiated across the display array. The first input circuit, second input circuit, control circuit, and output circuit serve universal functions that can be applied to multiple shift register stages, simplifying the manufacturing process through repetition and reducing the need for custom-designed complex circuits for each stage.
3Adaptability or versatility
If a cascade configuration with staggered clock signals is used to optimize shift register performance, then functionality and waveform capability are improved, but device complexity increases
Solution Approach 1:
The shift register utilizes periodic clock signals (first clock signal and second clock signal) that alternate in a staggered pattern to control the timing of signal propagation through the circuit stages. This periodic action enables the generation of various waveforms and maintains proper timing relationships in the cascade configuration without requiring complex additional control logic.
Data Source
AI summary
The present invention provides a shift register unit, a driving method, a driving circuit and a driving device. The shift register unit includes a first input circuit, a second input circuit, a control circuit and an output circuit; the first input circuit provides an input signal to a first node and provides a second voltage signal to a third node under control of a second clock signal; the second input circuit outputs a first voltage signal to the third node and controls a potential at a fourth node under control of a potential at the first node and an input control signal; the control circuit provides a first voltage signal to the first node under control of a potential at a fourth node. The present invention provides waveforms for operation of specific pixels.